Linear Clock Tree Topology for Dynamic Source Synchronous and Fully Synchronous 3-D Interfaces

Abstract

Reliable timing verification is a primary challenge in three-dimensional (3-D) integrated circuits. Process, temperature, and voltage variations between tiers within an integrated system introduce timing uncertainty into the clock and data paths, resulting in reduced operating speed. A clock tree topology that supports synchronous and source synchronous timing schemes is proposed for 3-D interfaces. The interface operates in a source synchronous scheme for fast data transfer and transitions to a synchronous scheme for bidirectional data flow. Phase compensation for the synchronous scheme is achieved via a delay locked loop.