Clock Tree Research Articles

A Reconfigurable Clock Polarity Assignment Flow for Clock Gated Designs

This paper presents a clock polarity assignment flow which permits post-silicon reconfigurability. The proposed method inserts xor gates at one level of the clock tree to facilitate the polarity assignment. The polarity of the xor gates can be reconfigured for different modes of clock gating (sleep mode, busy mode, etc.) such that a mode-specific reduction of the peak current can be achieved. Experimental results show that the worst case peak current on a clock tree can be reduced by 33.3% by assigning polarity to xor gates at the sink level of the clock tree. An additional 12.8% reduction in the worst case peak current can be achieved by reconfiguring the polarity assignment based on the clock gating information. The proposed flow increases the area by 7.1% but reduces both the total power consumption by 23.8% and the global skew increase (due to polarity assignment) from 19.3 to 8.8 ps. The insertion of xor gates at the non-sink nodes is also studied to further reduce the global skew increase and the area overhead.

SPECO: Stochastic Perturbation based Clock tree Optimization considering temperature uncertainty

Modern computing system applications or workloads can bring significant non-uniform temperature gradient on-chip, and hence can cause significant temperature uncertainty during clock-tree synthesis. Existing designs of clock-trees have to assume a given time-invariant worst-case temperature map but cannot deal with a set of temperature maps under a set of workloads. For robust clock-tree synthesis considering temperature uncertainty, this paper presents a new problem formulation: Stochastic PErturbation based Clock Optimization (SPECO). In SPECO algorithm, one nominal clock-tree is pre-synthesized with determined merging points. The impact from the stochastic temperature variation is modeled by perturbation (or small physical displacement) of merging points to offset the induced skews. Because the implementation cost is reduced but the design complexity is increased, the determination of optimal positions of perturbed merging points requires a computationally efficient algorithm.In this paper, one Non-Monte-Carlo (NMC) method is deployed to generate skew and skew variance by one-time analysis when a set of stochastic temperature maps is already provided. Moreover, one principal temperature–map analysis is developed to reduce the design complexity by clustering correlated merging points based on the subspace of the correlation matrix. As a result, the new merging points can be efficiently determined level by level with both skew and its variance reduced. The experimental results show that our SPECO algorithm can effectively reduce the clock-skew and its variance under a number of workloads with minimized wire-length overhead and computational cost.

Design of Low Power RISI Processor by Applying Clock Gating Technique

Power has become a primary consideration during hardware design. Dynamic power can contribute up to 50% of the total power dissipation. Clock-gating is the most common RTL optimization for reducing dynamic power. By applying Effective clock-gating technique on RISC processor adds additional logic to the existing synchronous circuit to prune the clock tree, thus disabling the portions of the circuitry that are not in use. Here in this project designed and developed efficient RISC CPU Interrupt controller unit ,Port controller and Program Flow Controller of an RISC Processor and clock gating technique applied to designed units. Combinational and Sequential clock-gating selectively suspend clocking while the block continues to produce output. In typical designs, combinational clockgating can reduce dynamic power by about 15-to20%.On the other hand sequential clock-gating can save significant power, typically reducing switching activity by 10-to-25% on a given block. Thus, different RTL techniques are used to reduce the power dissipation of a processor. The whole project captured in VHDL and implemented on targeted FPGA chip and observed the power using Xilinx Xpower tools.

다중 클록 영역의 SoC를 위한 효율적인 버퍼삽입 방식의 CTS에 대한 고려

본 논문에서는 버퍼 삽입 방법에 기반한 다중 클록 영역에서의 클록 트리 합성(clock tree synthesis, CTS) 기법에 대해서 논의한다. CTS를 수행하는데 있어서 준비해야하는 사항들과 실제적인 CTS 수행 방법들에 대해서 세부적인 기술들을 제안한다. 또한 CTS 수행 이후의 후처리 과정에 대해서도 제안한다. 버퍼 삽입 기반의 CTS는 기존에도 사용되는 방법인데 본 논문은 ASIC 및 SoC 상용 작업 현장에서 사용될 수 있는 실전적인 기법들에 대해서 논의하고자 한다. CTS는 사용되는 툴에 매우 의존적인데 본 논문은 Synopsys의 Astro를 대상으로 하였고, 이 툴을 이용하여 CTS를 수행하기 위한 세부적인 기술들에 대해서 이론을 바탕으로 경험적이고 고급적인 기법들을 제안한다. 본 논문을 통해 제안된 기법들은 많은 백앤드(backend) 설계자들에게 좋은 가이드가 될 것으로 기대한다. In this paper, we consider a clock tree synthesis technique (CTS) based on buffer insertion method in the multiple clock domain. We propose some detail techniques about the preparing items and the practical method for implementing CTS. We also propose a post processing after CTS implementation. Until now, the buffer insertion-based CTS technique has been widely used, and this paper discusses especially it's practical technique to be applied in the commercial fields to develop ASIC and SoC. CTS is very dependent on the used tool. We use Astro of Synopsys and propose the empirical and theoretical information of the detail techniques for implementing CTS using this tool. We expect that the proposed technique becomes to be good guidelines to backend designers.

Exploiting Programmable Temperature Compensation Devices to Manage Temperature-Induced Delay Uncertainty

This paper presents a new circuit technique to reduce temperature-induced delay uncertainty. Programmable temperature compensation devices (PTCDs) are used to tune logic gate pull-up and pull-down networks to their respective temperature-insensitive operating points, dramatically improving thermal resilience. Over a -55°C to 125°C temperature range, the proposed technique is shown to decrease temperature-induced delay uncertainty by up to 91% compared to other temperature resilient methods. We explore the limitations of using multi-VT and adaptive body biasing approaches to achieve temperature insensitivity; the proposed method achieves insensitive operation at larger supply voltages than prior methods, providing temperature insensitivity at nominal voltage for the first time. We explain how to integrate PTCDs into a variety of logic gates as well as larger structures such as a 1-bit mirror adder. Applying the proposed method to a clock tree is shown to reduce temperature-induced clock skew by up to 98%. Process variations degrade the temperature resilience; however, the proposed approach still improves temperature resilience by ~50% over prior methods when these variations are considered. Furthermore, we propose a process variation-compensation system to maintain our PTCD method's temperature resilience.

Analysis of multi-gigabits signal integrity through clock H-tree

The H-tree interconnect network is frequently used for the clock signal sharing in the microelectronic systems. Due to the increase of complexity and operating processing data speed, these interconnect effects can bottleneck the technological advancement. Hence, more accurate interconnect modelling methods are necessary for electronic designers. For this reason, a simple and accurate ultra-wide band (UWB) model of multilevel distributed interconnection clock trees as a single input multiple outputs (SIMO) system is developed in this article. Very accurate single input single output (SISO) model transfer functions are derived. This method allows the signal integrity prediction regarding the distributed H-tree characteristics including the source and load impedances. In order to demonstrate the relevance of model developed, analyses of two- and three-level tree networks were performed. Distributed H-tree realistic devices formed by sub-millimetre physical length lines for applications for standardised Printed Circuit Board (PCB) interconnections were experimented numerically. The piece of lines constituting the trees is modelled by UWB RLCG network from DC to 8 GHz which takes into account the frequency dispersions and dielectric loss effects. Thus, excellent correlations between simulations and the results from the models proposed were observed both in frequency and time domains regarding 2.5 Gbits/s clock input. Copyright © 2012 John Wiley & Sons, Ltd.

Technical Study on Low Power VLSI methods

In recent days every application must need power management. In this paper we presented a various techniques to handle the power management in IC. Power dissipation in a IC is base on power used by the IC and also by heat dissipation. To reduce energy use or to minimize heat dissipation some of the techniques are briefly discussed in this paper. Power management is becoming an increasingly urgent problem for almost every category of design and application, as power density, measured in watts per square millimeter, rises at an alarming rate. Power needs to be considered at the very early stages of a design, when the opportunity to save power is at a maximum. At the same time, making a design extremely power efficient results in trading off area and/or timing. For a Integrated Circuit (IC) perspective, effective energy management for a SoC (System-on-a-chip) must be built into the design starting at the architecture stage; and low-power techniques need to be employed at every stage of the design, from RTL (Register Transfer Level) to GDSII. This paper explains about the combination of techniques used for low power approach in integrated circuits (IC) or Chip Index Terms—Logic restructuring, Clock tree and clock Gating, Transistor Sizing, Pin swapping, multi-threshold voltage, Dynamic voltage scaling, DVFS, power gating, Memory splitting, Substrate biasing

Power-Driven Flip-Flop Merging and Relocation

We propose a power-driven flip-flop (FF) merging and relocation approach that can be applied after conventional timing-driven placement and before clock network synthesis. It targets to reduce the clock network size and thus the clock power consumption while controlling the switching power of the nets connected to the FFs by selectively merging FFs into multibit FFs and relocating them under timing and placement density constraints. The experimental results are very encouraging. For a set of benchmarks, our approach reduced the switching capacitance of clock network by 36%-43% after gated clock tree synthesis. Finally, the total switching capacitance of clock network and nets connected to the FFs is reduced by 24%-29%.

Obstacle-Aware Clock-Tree Shaping During Placement

Traditional integrated circuit (IC) design flows optimize clock networks before signal-net routing are limited by the quality of register placement. Existing publications also reflect this bias and focus mostly on clock routing. The few known techniques for register placement exhibit significant limitations and do not account for recent progress in large-scale placement and obstacle-aware clock-network synthesis. In this paper, we integrate clock network synthesis within global placement by optimizing register locations. We propose: 1) obstacle-aware virtual clock-tree synthesis; 2) arboreal clock-net contraction force with virtual-node insertion, which can handle multiple clock domains and gated clocks; and 3) an obstacle-avoidance force (OAF). Our work is validated on large benchmarks with numerous macroblocks. Experimental results indicate that our software implementation, called Lopper, prunes clock-tree branches to reduce their length by 30.0%-36.6% and average total dynamic power consumption by 6.8%-11.6% versus conventional wirelength-driven approaches. SPICE-driven simulations show that our methods improve robustness of clock trees.

Compact Expressions for Supply Noise Induced Period Jitter of Global Binary Clock Trees

Period jitter plays a critical role in global clock distribution design, because it directly impacts the time available for logic operations between sequential elements. Moreover, time-varying supply noise injected in global clock drivers can worsen the timing margin of critical paths by modulating period jitter. In the planning stage of global clock distribution for a high-end microprocessor, it is very critical to differentiate and understand the impacts of different design parameters on period jitter. However, it is hard to achieve due to complex relationship among different independent/dependent design parameters: supply noise amplitude, supply noise frequency, clock driver size, physical structures of interconnects, number of clock stages, temperature, process corners, etc.

Post-Placement Power Optimization With Multi-Bit Flip-Flops

Optimization for power is always one of the most important design objectives in modern nanometer integrated circuit design. Recent studies have shown the effectiveness of applying multi-bit flip-flops to save the power consumption of the clock network. This paper presents: 1) a novel design methodology of applying multi-bit flip-flops at the post-placement stage, which can be seamlessly integrated in modern design flow; 2) a new problem formulation for post-placement optimization with multi-bit flip-flops; 3) flip-flop clustering and placement algorithms to simultaneously minimize flip-flop power consumption and interconnecting wirelength; and 4) a progressive window-based optimization technique to reduce placement deviation and improve runtime efficiency of our algorithms. Experimental results show that our algorithms are very effective in reducing not only flip-flop power consumption but also clock tree and signal net wirelength. Consequently, the power consumption of the clock network is minimized.

A new clock network synthesizer for modern VLSI designs

In nanometer-scale VLSI physical design, clock tree becomes a major concern on determining the total performance of the chip. Both the clock skew and the PVT (process, voltage and temperature) variations contribute a lot to the behavior of the digital circuits. Previous works mainly focused on skew and wirelength minimization. However, it may lead to negative influence on the variation factors. In this paper, a novel clock tree synthesizer is proposed for performance improvement. Several algorithms are introduced to tackle the issues accordingly. A dual-MST geometric approach of perfect matching is developed for symmetric clock tree construction. In addition, a special technique of buffer sizing is also introduced. These two techniques can help balancing the tree structure in order to reduce the variation effect. An iterative buffer insertion technique and the dual-MZ blockage handling technique are also presented. They are developed for proper distribution of buffers and connection of wires, so the dynamic power consumption can be reduced. Additionally, slew table construction and internal nodes relocation are involved to satisfy the slew rate constraint and further reduce the clock skew. Experimental results show that the performance of our synthesizer is better than those of the previous works.

Asynchronous Bypass Channels for Multi-Synchronous NoCs: A Router Microarchitecture, Topology, and Routing Algorithm

Network-on-chip (NoC) designs have emerged as a replacement for traditional shared-bus designs for on-chip communication. As with all current very large scale integration designs, however, reducing power consumption in NoCs is a critical challenge. One approach to reduce power consumption is to dynamically scale the voltage and frequency of each network node or groups of nodes (DVFS). Another approach is to replace the balanced clock tree with a globally-asynchronous, locally-synchronous (GALS) clocking scheme. In both DVFS and GALS designs, the chip as a whole is multi-synchronous. As the NoCs interconnecting those nodes must communicate across these clock domain boundaries, they tend to have high latencies as packets must be synchronized at the intermediate nodes. In this paper, we propose a novel router microarchitecture which offers superior performance with respect to typical synchronizing router designs for multi-synchronous networks. Our approach features asynchronous bypass channels which allow flit traversal of intermediate nodes within the network without the latching or synchronization overheads of typical designs. We also propose a new network topology and routing algorithm that leverage the advantages of the bypass channel offered by our router design. We present a detailed analysis of design decisions which affect the performance of the asynchronous bypass channel network. Our experiments show that our design improves the performance of a conventional synchronizing design with similar resources by up to 26% at low loads and increases saturation throughput by up to 50% for a uniform random traffic.

Clock buffer polarity assignment with skew tuning

A clock polarity assignment method is proposed that reduces the peak current on the vdd/gnd rails of an integrated circuit. The impacts of (i) the output capacitive load on the peak current drawn by the sink-level clock buffers, and (ii) the buffer/inverter replacement scheme of polarity assignment on timing accuracy are considered in the formulation. The proposed sink-level-only polarity assignment is performed by a lexi-search algorithm in order to balance the peak current on the clock tree. Most of the previous polarity assignment methods that do not include clock tree resynthesis lead to an undesirable increase in the worst corner clock skew. Hence, a skew-tuning scheme is proposed that reduces the clock skew through polarity refinement and not through clock tree resynthesis. The proposed polarity assignment method with the skew-tuning scheme is implemented within an industrial design flow for practicality. Experimental results show that the worst-case peak current drawn by the clock tree can be reduced by an average of 36.5%. The worst corner clock skew is increased from 60.7ps to 76.2ps by applying the proposed polarity assignment method. The proposed skew-tuning scheme reduces the worst-case clock skew from 76.2ps to 61.5ps, on average, with a limited degradation in the peak current improvement (36.5% to 31.2%, on average).

Clock Tree synthesis for TSV-based 3D IC designs

For the cost-effective implementation of clock trees in through-silicon via (TSV)-based 3D IC designs, we propose core algorithms for 3D clock tree synthesis. For a given abstract tree topology, we propose DLE-3D ( d eferred l ayer e mbedding for 3D ICs), which optimally finds the embedding layers of tree nodes, so that the TSV cost required for a tree topology is minimized, and DME-3D ( d eferred m erge e mbedding for 3D ICs), which is an extended algorithm of the 2D merging segment, to minimize the total wirelength in 3D design space, with the consideration of the TSV effect on delay. In addition, when an abstract tree topology is not given, we propose NN-3D ( n earest n eighbor selection for 3D ICs), which constructs a (TSV and wirelength) cost-effective abstract tree topology for 3D ICs. Through experimentation, we have confirmed that the clock tree synthesis flow using the proposed algorithms is very effective, outperforming the existing 3D clock tree synthesis in terms of the number of TSVs, total wirelength, and clock power consumption.

Analysis and Design of Energy and Slew Aware Subthreshold Clock Systems

In this paper, we analyze the effect of clock slew in subthreshold circuits. Specifically, we address the issue that variations in clock slew at the register control can cause serious timing violations. We show that clock slew variations can cause frequency targets to deviate by as much as 28% from the design goals. Based on these observations, we recognize the importance of clock slew control in subthreshold circuits. We propose a systematic approach to design the clock tree for subthreshold circuits to reduce the clock slew variations while minimizing the energy dissipation in the tree. The combined approach, including the wire sizing and dynamic nodal capacitance control, can achieve better slew control (and better timing control) at lower energy in subthreshold circuits.

Discharge-path-based antenna effect detection and fixing for X-architecture clock tree

Antenna effect is a phenomenon in the plasma-based nanometer process and directly influences the manufacturing yield of VLSI circuits. Because antenna-critical metal wires have sufficient charges to damage the thin gate oxides of the clock input ports connected by a clock tree, the standard cells or IPs cannot be driven by the clock source synchronously. For a given X-architecture clock tree that connects n clock sinks, we consider the antenna effect in the clock tree and propose a discharge-path-based antenna effect detection method. To fix the antenna violations, we use the jumper insertion technique recommended by foundries. Furthermore, we integrate the layer assignment technique to reduce the inserted jumper and via counts. Differing from the existing works, the delay of vias is considered in delay calculation, and a wire sizing technique is applied for clock skew compensation after fixing the antenna violations. Experimental results on benchmarks show that our algorithm runs in O(n 2) to averagely insert 48.21% less jumpers and reduce 20.35% in vias compared with other previous algorithms. Moreover, the SPICE simulation further verifies the correctness of the resulting clock tree.

Robust Chip-Level Clock Tree Synthesis

Chip-level clock tree synthesis (CCTS) is a key problem that arises in complex system-on-a-chip designs. A key requirement of CCTS is to balance the clock-trees belonging to different IPs such that the entire tree has a small skew across all process corners. Achieving this is difficult because the clock trees in different IPs might be vastly different in terms of their clock structures and cell/interconnect delays. The chip-level clock tree is expected to compensate for these differences and achieve good skews across all corners. Also, CCTS is expected to reduce clock divergence between IPs that have critical timing paths between them. Reducing clock divergence reduces the maximum possible clock skew in the critical paths between the IPs and thus improves yield. This paper proposes effective CCTS algorithms to simultaneously reduce multicorner skew and clock divergence. Experimental results on several test-cases indicate that our methods achieve 30% reduction in the clock divergence with significantly improved multicorner skew variance, at the cost of 2% increase in buffer area and 1% increase in wirelength.

Autonomous, Multilevel Ring Tuning Scheme for Post-Silicon Active Clock Deskewing Over Intra-Die Variations

Synchronous clock distribution continues to be the dominant timing methodology for VLSI circuit designs. As processes shrink, clock speeds increase, and die sizes grow, an increasingly larger percentage of the clock period is being lost to skew and jitter budgets. Process, voltage, and temperature variations, especially those that are intra-die, increasingly upset the distribution of a synchronized clock signal, even in properly balanced clock tree networks. As a result, active clock deskewing systems are becoming necessary to tune out unwanted clock skew after chip fabrication. This paper first defines the operation of a specially designed phase detector, referred to as an up/down detector (UDD). Next, four of these UDDs are used as links to construct a stable, autonomously locking quadrantal ring tuning (QRT) configuration that effectively joins together four distributed delay-locked loops (DLLs) without the need for any system-level controller. This cyclic, self-controlled, quad-DLL ring tuning technique is then implemented hierarchically to dynamically adjust clock signal delays across an entire chip during normal circuit operation. A simplistic two-level QRT system is presented for a generic H-tree clock distribution network, demonstrating stable locking behavior and more than 50% average reduction in overall clock skew.

Robust Clock Network Design Methodology for Ultra-Low Voltage Operations

Robust design is a critical concern in ultra-low voltage operation due to large sensitivities to process and environmental variations. In particular, clock networks require careful attention to ensure robust distribution of well-defined clock signals to avoid setup and hold time violations. In this paper, we propose two complementary methodologies to design robust and low power clock networks at ultra-low voltage regimes, an un-buffered and buffered approach, which can be chosen from depending on the significance of wire resistance. We confirm the efficacy of the proposed strategies through simulations with test circuits over different supply voltages, technologies, and design sizes. We also perform case studies of low voltage clock network design for a microprocessor and signal processing core. For one case study, we employ the un-buffered methodology, reducing +2 σ skew by ~ 5000 × and +2 σ slew by ~ 15% without energy overhead, compared to conventional 1-level buffered H-trees. In the other case, a 3-level buffered tree is implemented, with the proposed clock tree reducing +2 σ skew to ~ 2 % of a clock cycle ( 0.68 × fanout-of-4 delay) and slew variability (σ/μ) to 0.08 at V.