Clock Tree Research Articles

Cross-Mesh Clock Network Synthesis

In the clock network design, the trade-off between power consumption and timing closure is an important and difficult issue. The clock tree architecture has a shorter wire length and better power consumption, but it is more difficult to achieve timing closure with it. On the other hand, clock mesh architecture is easier to satisfy the clock skew constraint, but it usually has much more power consumption. Therefore, a hybrid clock network architecture that combines both the clock tree and clock mesh seems to be a promising solution. In a normal hybrid mesh/tree structure, a driving buffer is placed in the intersection of mesh lines. In this paper, we propose a novel cross-mesh architecture, and we distribute the buffers to balance the overall switching capacitance, reducing the number of registers connected to a subtree, and the load capacitance of a buffer. With the average dispersion of the overall driving force, our methodology creates small non-zero skew clock trees. In addition, we integrate clock gating, register clustering, and load balancing techniques to optimize clock skew and load capacitance simultaneously. The proposed methodology has four stages: cross-mesh planning, register clustering, mesh line connecting, and load balancing. Experimental results show that our cross-mesh architecture has high tolerance for process variation, and is robust in all the operation modes. Comparing it to the uniform mesh architecture, our methodology and algorithms reduce 28.9% of load capacitance and 80.4% of clock skew on average. Compared to the non-uniform mesh architecture, we also reduce capacitance by 22.4% and skew by 76.7% on average. This illustrates that we can obtain a feasible solution effectively and improve both power consumption and clock skew simultaneously.

Linear Clock Tree Topology for Dynamic Source Synchronous and Fully Synchronous 3-D Interfaces

Reliable timing verification is a primary challenge in three-dimensional (3-D) integrated circuits. Process, temperature, and voltage variations between tiers within an integrated system introduce timing uncertainty into the clock and data paths, resulting in reduced operating speed. A clock tree topology that supports synchronous and source synchronous timing schemes is proposed for 3-D interfaces. The interface operates in a source synchronous scheme for fast data transfer and transitions to a synchronous scheme for bidirectional data flow. Phase compensation for the synchronous scheme is achieved via a delay locked loop.

An 82-nW 0.53-pJ/SOP Clock-Free Spiking Neural Network With 40-μs Latency for AIoT Wake-Up Functions Using a Multilevel-Event-Driven Bionic Architecture and Computing-in-Memory Technique

This article presents a clock-free spiking neural network (SNN) intelligent inference engine (IIE) for artificial intelligence of things (AIoT) sensor nodes, which often operate in random-sparse-event (RSE) scenarios. The IIE drastically reduces the system’s long-term average (LTA) power consumption, improves energy efficiency, and achieves microsecond level inference latency. Three techniques are proposed: 1) A clock-free SNN architecture without clock tree, frame generator, and arbiter, is driven by the output spikes, which are encoded with level-crossing (LC) sampling method; the circuit activity is completely related to event activity and spike rates, dramatically reducing the overall power consumption and latency. 2) The bioinspired leaky-integrate-fire (LIF) neurons directly extract the time-domain information from asynchronous spikes, reducing the network size and number of operations. 3) The computing-in-memory (CIM) and mixed-signal synapse-neuron circuits are employed to increase the SNN parallelism and avoid weight movements, thus improving the energy efficiency and response speed. The measured LTA power is bounded at 82 nW while the event-driven chip is on call and waiting for events; the energy efficiency is 0.53 pJ per synapse operation (SOP), only 1/3 that of state-of-the-art methods at 4bit weights even with 180 nm technology. We demonstrate electrocardiogram (ECG) recognition as a typical AIoT application, and the power consumption is less than 350 nW. The measured accuracy of abnormal ECG detection is 90.5%. Moreover, the latency is only 40 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula> s to realize real-time NN inference. This work provides an effective solution for AIoT nodes that require both ultralow power and fast response.

Clock-Latency-Aware Fault-Tolerant DLL for Multi-Die Clock Synchronization

A Delay-Locked Loop (DLL) circuit is indispensable for clock synchronization in a chip incorporating several heterogeneous dice. It has been shown previously that a fault and soft-error tolerant DLL can be achieved by Triple-Module Redundancy (TMR) enhanced with a timing correction scheme. However, the prior work still has a severe limitation -it does not consider the latency of the clock tree, and this limitation will make it infeasible in realistic situations. We demonstrate in this paper that this limitation can be overcome by a new “clock-latency-aware” architecture, thereby making a fault and soft-error-tolerant DLL truly realistic.

Random Forest-based Thermal Effect Prediction for Clock Tree Synthesis in 3D-IC

Random Forest-based Thermal Effect Prediction for Clock Tree Synthesis in 3D-IC

Design and Optimization of 4-Bit Array Multiplier with Adiabatic Logic Using 65 nm CMOS Technologies

ABSTRACT This paper proposes a 4-bit array multiplier useful in the design of basically mixer circuit, which is highly involved in signal and image processing using an efficient low-power VLSI technique. The presented architecture is completely implemented adiabatic techniques in the Near Threshold Region, which optimize the product of propagation delay and power dissipation. Multiplier is the most frequently used element in many digital electronics applications. Depending on the applications, various types of multipliers emerge. With this technique, the total power dissipation, i.e. dynamic power dissipation as well as static power dissipation is less as compared to the conventional CMOS technique. The Near Threshold Adiabatic Logic (NTAL) technique is used with a single timevarying power supply which reduces the clock tree management and enhances the energy-saving capability. Simulation of the proposed design is done by Cadence virtuoso schematic editor with specter simulator on TSMC 65 nm technology node to verify the optimized result. Also comparing our result to conventional CMOS techniques with all the same design parameters, the result shows that power dissipation improvement of approximately 66.6%, 14.4%, and 64.6% with respect to varying frequency, supply voltage, and load capacitance with other parameters keep constant such as if the frequency is varying than capacitance load value is C load = 10 pF and V DD(max) = 1.2 V, similarly if the supply voltage is varying than capacitance load value is C load = 10 pF and frequency F = 4 GHz and if load capacitance is varying than frequency F = 4 GHz and supply voltage V DD(max) = 1.2 V.

A Local Optimization Method for Single Flux Quantum Logic Circuits Design Utilizing Synchronizer IPs

In the post-Moore era, slow-growing operating frequency and massive power dissipation make researchers seek new developing directions in integration circuits (ICs). The single flux quantum (SFQ) circuit, a type of superconducting digital circuit, is regarded as an alternative circuit for future computing technology. SFQ circuits are natural gate-level-pipelining synchronous sequential circuits requiring path balancing. However, path balancing may consume enormous resources, as the logic levels of fan-in gates of most gates are different, with the consumption originating from the extra gates (D-Flip-Flops, DFFs) for path balancing and the routing with a much larger clock tree. Hence, in this article, we propose a local optimization method to address the vast consumption problem of the clock tree caused by path balancing in SFQ circuits, primarily relying on self-developed electronic design automation tools for the JSICcomplier for SFQ circuits and using the SIMIT Nb03 cell library. Moreover, we design synchronizer IPs called Dsyn series to replace DFFs in path balancing. The clock nodes and the clocking path consumption are highly reduced by utilizing the proposed strategy, while the new series can be recognized as IPs and easily added to our library, affording scalability. Experiments in a demo S-box circuit demonstrated a percentage of Josephson junctions reduction in clock tree up to 36.48%, while on a few benchmark circuits, the corresponding results are up to 50.69%, demonstrating our method's effectiveness.

Comparing the transmission potential from sequence and surveillance data of 2009 North American influenza pandemic waves.

Technological advancements in phylodynamic modeling coupled with the accessibility of real-time pathogen genetic data are increasingly important for understanding the infectious disease transmission dynamics. In this study, we compare the transmission potentials of North American influenza A(H1N1)pdm09 derived from sequence data to that derived from surveillance data. The impact of the choice of tree-priors, informative epidemiological priors, and evolutionary parameters on the transmission potential estimation is evaluated. North American Influenza A(H1N1)pdm09 hemagglutinin (HA) gene sequences are analyzed using the coalescent and birth-death tree prior models to estimate the basic reproduction number (R 0 ). Epidemiological priors gathered from published literature are used to simulate the birth-death skyline models. Path-sampling marginal likelihood estimation is conducted to assess model fit. A bibliographic search to gather surveillance-based R 0 values were consistently lower (mean≤1.2) when estimated by coalescent models than by the birth-death models with informative priors on the duration of infectiousness (mean≥1.3 to ≤2.88 days). The user-defined informative priors for use in the birth-death model shift the directionality of epidemiological and evolutionary parameters compared to non-informative estimates. While there was no certain impact of clock rate and tree height on the R 0 estimation, an opposite relationship was observed between coalescent and birth-death tree priors. There was no significant difference (p=0.46) between the birth-death model and surveillance R 0 estimates. This study concludes that tree-prior methodological differences may have a substantial impact on the transmission potential estimation as well as the evolutionary parameters. The study also reports a consensus between the sequence-based R 0 estimation and surveillance-based R 0 estimates. Altogether, these outcomes shed light on the potential role of phylodynamic modeling to augment existing surveillance and epidemiological activities to better assess and respond to emerging infectious diseases.

Mix &amp; Latch: An Optimization Flow for High-Performance Designs With Single-Clock Mixed-Polarity Latches and Flip-Flops

Flip-flops are the most used sequential elements in synchronous circuits, but designs based on latches can operate at higher frequencies and occupy less area. Techniques to increase the maximum operating frequency of flip-flop based designs, such as time-borrowing, rely on tight hold constraints that are difficult to satisfy using traditional back-end optimization techniques. We propose <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Mix &amp; Latch</i> , a methodology to increase the operating frequency of synchronous digital circuits using a single clock tree and a mixed distribution of positive- and negative-edge-triggered flops, and positive- and negative-level-sensitive latches. An efficient mathematical model is proposed to optimize the type and location of the sequential elements of the circuit. We ensure that the initial registers are not moved from their initial location, although they may change type, thus allowing the use of equivalence checking and static timing analysis to verify formally the correctness of the transformation. The technique is validated using a 28nm CMOS FDSOI technology, obtaining 1.33X post-layout average operating frequency improvement on a broad set of benchmarks over a standard commercial design flow. Additionally, the circuit area was also reduced by more than 1.19X on average for the same benchmarks, although the overall area reduction is not a goal of the optimization algorithm. To the best of our knowledge, this is the first work that proposes combining mixed-polarity flip-flops and latches to improve the circuit performance.

VLSI Placement Optimization Algorithms

Placement is a fundamental optimization step to compute cell locations. The quality of results in Clock Tree Synthesis (CTS) and routing stages is impacted by the placement solution. The placement optimization flow is split into (1)global placement, (2) legalization, and (3) detailed placement. In global placement, cell locations are computed to minimize total wire length subject to a maximum cell density threshold. The cell overlapping and cell alignment to site row boundaries are relaxed. In legalization, cells are placed in locations free of overlapping and aligned to site row boundaries. Legalization algorithms compute cell locations with minimized cell displacement. In detailed placement, objectives are optimized locally. Detailed placement algorithms iterate over one cell or a small set of cells. The traditional optimization objective is total wire length. Placement algorithms also address timing violations, routability, design rules, and so forth. The placement algorithms rely on heuristics and formal methods to compute optimized cell locations. Moreover, placement algorithms require models to address signal delay propagation, area density, routing congestion, hyper-edge nets, and so forth. In the literature, several algorithms have been presented to improve placement solutions. On the other hand, placement is a really challenging problem that continues to have space for further improvement and for innovative algorithms.

Analysis of the genome of grapevine red blotch virus and related grabloviruses indicates diversification prior to the arrival of Vitis vinifera in North America.

In this study 163 complete whole-genome sequences of the emerging pathogen grapevine red blotch virus (GRBV; genus Grablovirus, family Geminiviridae) were used to reconstruct phylogenies using Bayesian analyses on time-tipped (heterochronous) data. Using different combinations of priors, Bayes factors identified heterochronous datasets (3×200 million chains) generated from strict clock and exponential tree priors as being the most robust. Substitution rates of 3.2×10-5 subsitutions per site per year (95% HPD 4.3-2.1×10-5) across the whole of the GRBV genome were estimated, suggesting ancestral GRBV diverged from ancestral wild Vitis latent virus 1 around 9 000 years ago, well before the first documented arrival of Vitis vinifera in North America. Whole-genome analysis of GRBV isolates in a single infected field-grown grapevine across 12 years identified 12 single nucleotide polymorphisms none of which were fixed substitutions: an observation not discordant with the in silico estimate. The substitution rate estimated here is lower than those estimated for other geminiviruses and is the first for a woody-host-infecting geminivirus.

A High-Level Approach for Energy Efficiency Improvement of FPGAs by Voltage Trimming

Chip manufacturers define voltage margins on top of the “best-case” operational voltage of their chips to ensure reliable functioning in the worst-case settings. The margins guarantee correctness of operation, but at the cost of performance and power efficiency. Violating the margins is tempting to save energy, but might lead to timing errors. This article proposes an algorithmic solution that enables reliable removal of the margins by detecting errors on the fly. In contrast to previous approaches that require special hardware to detect timing errors, the proposed method is fully implementable using high-level synthesis tools without reliance on additional hardware. The approach is demonstrated using a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$32 \times 32$ </tex-math></inline-formula> matrix-matrix multiplication and a simple multilayer neural network implemented on two Xilinx ZC702 field-programmable gate array (FPGA) System-on-Chip (SoC) platforms, showcasing its utility in detecting errors that may originate from different sources of logic circuits, clock tree, or memory. Results show that the energy dissipation is halved, while the implementation is clocked at 2.5x faster than specified by the design tool of the vendor.

QuCTS—Single-Flux Quantum Clock Tree Synthesis

Superconductive rapid single-flux quantum (RSFQ) is an emerging cryogenic technology, promising a significant boost in performance and ultralow power consumption. The operating frequency achieved by RSFQ digital integrated circuits is several orders of magnitude greater than traditional CMOS circuits. The fundamental difference of RSFQ circuits, however, renders traditional clocking techniques appropriate for CMOS unsuitable for RSFQ technology. Most RSFQ logic gates, such as AND and OR, are sequential in nature. The number of pipeline stages is therefore significantly greater in RSFQ as compared to CMOS, complicating the clock distribution network design process. This issue is further exacerbated with the need for splitters to achieve a fanout greater than one and the need for transmission lines rather than ordinary metallic wires as in CMOS. In this work, QuCTS—single-flux Quantum (SFQ) Clock Tree Synthesis—is presented. QuCTS utilizes a two-stage framework for synthesizing clock networks. In the clock skew scheduling stage, the clock signal arrival time of each gate is chosen to maximize the robustness of the circuit to timing variations. In the clock tree synthesis stage, the layout of the clock distribution network is generated based on a novel delay equilibration technique. QuCTS is the first clock tree synthesis tool for RSFQ circuits utilizing useful clock skew. The synthesized network satisfies the clock arrival time requirements while minimizing the associated overhead, such as the interconnect length and number of delay elements. The tool is validated on a set of benchmark circuits. In a prototypical case study, a clock tree is generated for the AMD2901 with 1049 clock sinks in 53 min while satisfying the clock arrival time.

A Clock Tree Prediction and Optimization Framework Using Generative Adversarial Learning

Modern physical design flows highly depend on design space exploration to find the commercial tools’ clock tree synthesis (CTS) parameters that lead to optimized clock trees. However, such exploration is often time-consuming and computationally inefficient. In this article, we overcome this drawback by proposing a novel framework named GAN-CTS, which utilizes conditional generative adversarial network (GAN) to predict and optimize CTS outcomes. Our framework is built upon three sequential learning stages. First, to precisely characterize distinct designs, we leverage transfer learning to extract netlist features directly from placement images. Second, we perform regression learning using various methods to predict the target CTS outcomes and demonstrate that the proposed multitask learning approach achieves better accuracy than the meta-modeling method adopted by previous works. To fully benefit from the predictions made by our framework, we further quantitatively interpret the importance of each CTS input parameter subject to various design objectives through attribution-based learning. Finally, generative adversarial learning is leveraged to optimize the target clock metrics with the guidance provided by the pretrained regression model. To substantiate the generality of our framework, we perform validations on four unseen netlists that are not utilized in the training process. The experimental results conducted on real-world designs demonstrate that our framework: 1) achieves an average prediction error of 3%; 2) improves the commercial tool’s auto-generated clock tree by 20.7% in clock power, 21.5% in clock wirelength, 36.1% in the worst skew; and 3) reaches an F1-score of 0.93 in the classification task of determining successful and failed CTS runs.

Programmable Local Clock SET Filtering for SEE-Resistant FPGA

This brief presents a new clock-related <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Single-Event Effect</i> (SEE) mitigation method for <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Field Programmable Gate Arrays</i> (FPGAs). SEEs are most likely to happen in harsh environments, such as space, and are decently mitigated with <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Triple Modular Redundancy</i> (TMR). However, clock tree triplication has a high cost for FPGAs; it reduces the total amount of usable clocks and introduces uncontrolled skew variation. Therefore, we propose to instantiate a <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Programmable Local Clock Filter</i> (PLCF) close to TMRed sequential elements to locally triplicate the clock and filter the SEEs coming from the clock tree. The PLCF mitigation method has demonstrated 100% resilience to SEEs, which target either the clock tree or the PLCF’s logic. Thus, PLCF represents the first programmable clock-related SEE mitigation method and proposes a promising alternative to the state-of-the-art technics applied to FPGAs’ fabric.

A Novel Clock Tree Aware Placement Methodology for Single Flux Quantum Logic Circuits With Maximum Path Length Consideration

In a single-flux-quantum (SFQ) circuit, almost all cells need to receive the clock signal that incurs a high clock routing overhead. Besides, the clock tree of an SFQ circuit requires the insertion of a clock splitter cell at every tree branching point that renders the conventional design flow of placement followed by clock tree synthesis (CTS) ineffective to obtain a high quality clock tree with low clock skew. Moreover, very few works in the literature attempted to minimize the maximum path length during SFQ circuit placement. The maximum path length, which is the length of the longest source-to-sink path of any data signal, should be minimized to achieve a higher final performance and to reduce the overhead for length matching in subsequent routing. To address these issues, we propose a two-stage global placement methodology and a placement refinement algorithm after placement legalization. Our two-stage global placement methodology first applies a conventional global placement algorithm to place the cells in the given SFQ circuit evenly, which is followed by CTS and clock splitter insertion, and then, performs a second stage of global placement to replace both the original cells and clock splitters at the same time. In the second global placement stage, the look-ahead legalization technique is used to spread out the original cells and the clock splitters, and the clock tree is resynthesized several times to obtain an optimized clock tree topology such that there are little overlaps of the clock splitters with the original circuit cells. We propose a novel net model in global placement that facilitates the concurrent optimization of the total wirelength and the maximum path length. After legalizing the placement of all cells, a specialized placement refinement method is run to further reduce the clock skew and the maximum path length. Compared with the previous state-of-the-art work, on average, we reduced the total half-perimeter wirelength by 9%, reduced the maximum path length by 58%, and reduced the clock skew by 32%.

Synthesis of Clock Networks with a Mode-Reconfigurable Topology

Modern digital circuits are often required to operate in multiple modes to cater to variable frequency and power requirements. Consequently, the clock networks for such circuits must be synthesized, meeting different timing constraints in different operational modes. The overall power consumption and robustness to variations of a clock network are determined by the topology. However, state-of-the-art clock networks use the same topology in every mode, despite that timing constraints in low- and high-performance modes can be very different. In this article, we propose a clock network with a mode-reconfigurable topology (MRT) for circuits with positive-edge-triggered sequential elements. In high-performance modes, the MRT structure is reconfigured into a near-tree to provide the required robustness to variations. In low-performance modes, the MRT structure is reconfigured into a tree to save power. Non-tree (or near-tree) structures provide robustness to variations by appropriately constructing multiple alternative paths from the clock source to the clock sinks, which neutralizes the negative impact of variations. In MRT structures, OR-gates are used to join multiple alternative paths into a single path. Hence, the MRT structures consume no short-circuit power because there is only one gate driving each net. Moreover, it is straightforward to reconfigure an MRT structure into a tree topology using a single clock gate. In high-performance modes, the experimental results demonstrate that MRT structures have \( 25\% \) lower power consumption than state-of-the-art near-tree structures. In low-performance modes, the power consumption of the MRT structure is similar to the power consumption of a clock tree.

On-Chip Structures for Fmax Binning and Optimization.

Process variations during manufacturing lead to differences in the performance of the chips. In order to better utilize the performance of the chips, it is necessary to perform maximum operation frequency () tests to place the chips into different speed bins. For most tests, significant efforts are put in place to reduce test cost and improve binning accuracy; e.g., our conference paper published in ICICM 2017 presents a novel binning sensor for low-cost and accurate speed binning. However, by promoting chips placed at the lower bins, because of conservative binning, into higher bins, the overall profit can greatly increase. Therefore, this paper, extended based on a conference paper, presents a novel and adaptive methodology for speed binning, in which the paths impacting the speed bin of a specific IC are identified and adapted by our proposed on-chip Binning Checker and Binning Adaptor. As a result, some parts at a bin margin can be promoted to higher bins. The proposed methodology can be used to optimize the yield of a digital circuit when it has redundant timing in clock tree, and it can be integrated into current tests with low extra cost. The proposed adaptive system has been implemented and validated on five benchmarks from ITC, ISCAS89, and OpenSPARCT2 core on 28 nm Altera FPGAs. Measurement results show that the number of higher bin chips is improved by 7–16%, and our cost analysis shows that the profit increase is between 1.18% and 3.04%.

Clock-Latency-Aware Pre-CTS for better Timing Closure in VLSI Design

A common strategy for reducing the time jump due to a clock tree insertion is to add a clock uncertainty value. If a small clock uncertainty value is selected for the Pre-CTS optimization, then a significant timing jump is observed when the clock tree is inserted, and clock timings are propagated. On the other hand, if the clock uncertainty is large, then the place and route (PNR) flow does not converge. This approach has been proven to be insufficient as each timing path is affected differently by the creation of the clock tree. In this paper, we suggest a more targeted approach whereby all pins in the clock tree will be annotated with their estimated latency, and therefore clock arrival times under ideal clocks should closely model the post-CTS arrival times. This objective is achieved by introducing an accurate and fast clock prediction early in the flow at the pre-CTS stage. As a result, the transition from the pre-CTS stage to the post-CTS stage becomes easier without significant timing jumps. An experiment on nine commercial test cases led to a significant TNS timing improvement of up to 68%, with an average of 35% at the end of the route stage. The full PNR flow runtime is not impacted. We achieved a 3% average runtime reduction over all test cases. Keywords—Clock-latency estimation, Clock-tree Synthesis, Integrated circuit conception, Physical implementation, Static timing analysis, Static timing closure.

Improved result of TSV and Slew aware 3D Gated Clock Tree Synthesis using charge recycling configuration

Improved result of TSV and Slew aware 3D Gated Clock Tree Synthesis using charge recycling configuration