CLIC Vertex Detector Research Articles

Performance evaluation of thin active-edge planar sensors for the CLIC vertex detector

Thin planar silicon sensors with a pitch of 55µm, active edge and various guard-ring layouts are investigated, using two-dimensional finite-element T-CAD simulations. The simulation results have been compared to experimental data, and an overall good agreement is observed. It is demonstrated that the 50µm thick active-edge planar silicon sensors with floating guard-ring or without guard-ring can be operated fully efficiently up to the physical edge of the sensor. The simulation findings are used to identify suitable sensor designs for application in the high-precision vertex detector of the future CLIC linear e+e− collider.

Pixel detector R&D for the Compact Linear Collider

The physics aims at the proposed future CLIC high-energy linear e+ e− collider pose challenging demands on the performance of the detector system. In particular the vertex and tracking detectors have to combine precision measurements with robustness against the expected high rates of beam-induced backgrounds. A spatial resolution of a few microns and a material budget down to 0.2% of a radiation length per vertex-detector layer have to be achieved together with a few nanoseconds time stamping accuracy. These requirements are addressed with innovative technologies in an ambitious detector R&D programme, comprising hardware developments as well as detailed device and Monte Carlo simulations based on TCAD, Geant4 and Allpix2. Various fine pitch hybrid silicon pixel detector technologies are under investigation for the CLIC vertex detector. The CLICpix and CLICpix2 readout ASICs with 25 μm pixel pitch have been produced in a 65 nm commercial CMOS process and bump-bonded to planar active edge sensors as well as capacitively coupled to High-Voltage (HV) CMOS sensors. Monolithic silicon tracking detectors are foreseen for the large surface (≈ 140 m2) CLIC tracker. Fully monolithic prototypes are currently under development in High-Resistivity (HR) CMOS, HV-CMOS and Silicon on Insulator (SOI) technologies. The laboratory and beam tests of all recent prototypes profit from the development of the CaRIBou universal readout system. This paper presents an overview of the CLIC pixel-detector R&D programme, focusing on recent test-beam and simulation results.

Tracking performance and simulation of capacitively coupled pixel detectors for the CLIC vertex detector

In order to achieve the challenging requirements on the CLIC vertex detector, a range of technology options have been considered in recent years. One prominent idea is the use of active sensors implemented in a commercial high-voltage CMOS process, capacitively coupled to hybrid pixel readout chips. Recent results have shown the approach to be feasible, though more detailed studies of the performance of such devices, including simulation, are required. The CLICdp collaboration has developed a number of ASICs as part of its vertex detector R&D programme, and here we present results on the performance of a CCPDv3 active sensor glued to a CLICpix readout chip. Charge collection characteristics and tracking performance have been measured over the full expected angular range of incident particles using 120 GeV/c secondary hadron beams from the CERN SPS. Single hit efficiencies have been observed above 99% in the full range of track incidence angles, down to shallow angles. The single hit resolution has also been observed to be stable over this range, with a resolution around 6 $\mu$m. The measured charge collection characterstics have been compared to simulations carried out using the Sentaurus TCAD finite-element simulation package combined with circuit simulations and parametrisations of the readout chip response. The simulations have also been successfully used to reproduce electric fields, depletion depths and the current-voltage characteristics of the device, and have been further used to make predictions about future device designs.

Characterisation of capacitively coupled HV/HR-CMOS sensor chips for the CLIC vertex detector

The capacitive coupling between an active sensor and a readout ASIC has been considered in the framework of the CLIC vertex detector study. The CLICpix Capacitively Coupled Pixel Detector (C3PD) is a High-Voltage CMOS sensor chip produced in a commercial 180 nm HV-CMOS process for this purpose. The sensor was designed to be connected to the CLICpix2 readout chip. It therefore matches the dimensions of the readout chip, featuring a matrix of 128×128 square pixels with 25μm pitch. The sensor chip has been produced with the standard value for the substrate resistivity (∼20 Ωcm) and it has been characterised in standalone testing mode, before receiving and testing capacitively coupled assemblies. The standalone measurement results show a rise time of ∼20 ns for a power consumption of 5μW/pixel. Production of the C3PD HV-CMOS sensor chip with higher substrate resistivity wafers (∼20, 80, 200 and 1000 Ωcm) is foreseen. The expected benefits of the higher substrate resistivity will be studied using future assemblies with the readout chip.

Design and standalone characterisation of a capacitively coupled HV-CMOS sensor chip for the CLIC vertex detector

The concept of capacitive coupling between sensors and readout chips is under study for the vertex detector at the proposed high-energy CLIC electron positron collider. The CLICpix Capacitively Coupled Pixel Detector (C3PD) is an active High-Voltage CMOS sensor, designed to be capacitively coupled to the CLICpix2 readout chip. The chip is implemented in a commercial 180 nm HV-CMOS process and contains a matrix of 128×128 square pixels with 25μm pitch. First prototypes have been produced with a standard resistivity of ∼20 Ωcm for the substrate and tested in standalone mode. The results show a rise time of ∼20 ns, charge gain of 190 mV/ke− and ∼40 e− RMS noise for a power consumption of 4.8μW/pixel. The main design aspects, as well as standalone measurement results, are presented.

Silicon technologies for the CLIC vertex detector

CLIC is a proposed linear e+e- collider designed to provide particle collisions at center-of-mass energies of up to 3 TeV. Precise measurements of the properties of the top quark and the Higgs boson, as well as searches for Beyond the Standard Model physics require a highly performant CLIC detector. In particular the vertex detector must provide a single point resolution of only a few micrometers while not exceeding the envisaged material budget of around 0.2% X0 per layer. Beam-beam interactions and beamstrahlung processes impose an additional requirement on the timestamping capabilities of the vertex detector of about 10 ns. These goals can only be met by using novel techniques in the sensor and ASIC design as well as in the detector construction.The R&D program for the CLIC vertex detector explores various technologies in order to meet these demands. The feasibility of planar sensors with a thickness of 50–150 μm, including different active edge designs, are evaluated using Timepix3 ASICs. First prototypes of the CLICpix readout ASIC, implemented in 65 nm CMOS technology and with a pixel size of 25×25μm 2, have been produced and tested in particle beams. An updated version of the ASIC with a larger pixel matrix and improved precision of the time-over-threshold and time-of-arrival measurements has been submitted. Different hybridization concepts have been developed for the interconnection between the sensor and readout ASIC, ranging from small-pitch bump bonding of planar sensors to capacitive coupling of active HV-CMOS sensors. Detector simulations based on Geant 4 and TCAD are compared with experimental results to assess and optimize the performance of the various designs.This contribution gives an overview of the R&D program undertaken for the CLIC vertex detector and presents performance measurements of the prototype detectors currently under investigation.

Capacitively coupled hybrid pixel assemblies for the CLIC vertex detector

The vertex detector at the proposed CLIC multi-TeV linear e+e− collider must have minimal material content and high spatial resolution, combined with accurate time-stamping to cope with the expected high rate of beam-induced backgrounds. One of the options being considered is the use of active sensors implemented in a commercial high-voltage CMOS process, capacitively coupled to hybrid pixel ASICs. A prototype of such an assembly, using two custom designed chips (CCPDv3 as active sensor glued to a CLICpix readout chip), has been characterised both in the lab and in beam tests at the CERN SPS using 120GeV/c positively charged hadrons. Results of these characterisation studies are presented both for single and dual amplification stages in the active sensor, where efficiencies of greater than 99% have been achieved at −60V substrate bias, with a single hit resolution of 6.1μm. Pixel cross-coupling results are also presented, showing the sensitivity to placement precision and planarity of the glue layer.

The CLIC Vertex Detector

The precision physics needs at TeV-scale linear electron-positron colliders (ILC and CLIC) require a vertex-detector system with excellent flavour-tagging capabilities through a measurement of displaced vertices. This is essential, for example, for an explicit measurement of the Higgs decays to pairs of b-quarks, c-quarks and gluons. Efficient identification of top quarks in the decay t → Wb will give access to the ttH-coupling measurement. In addition to those requirements driven by physics arguments, the CLIC bunch structure calls for hit timing at the few-ns level. As a result, the CLIC vertex-detector system needs to have excellent spatial resolution, full geometrical coverage extending to low polar angles, extremely low material budget, low occupancy facilitated by time-tagging, and sufficient heat removal from sensors and readout. These considerations challenge current technological limits. A detector concept based on hybrid pixel-detector technology is under development for the CLIC vertex detector. It comprises fast, low-power and small-pitch readout ASICs implemented in 65 nm CMOS technology (CLICpix) coupled to ultra-thin planar or active HV-CMOS sensors via low-mass interconnects. The power dissipation of the readout chips is reduced by means of power pulsing, allowing for a cooling system based on forced gas flow. This contribution reviews the requirements and design optimisation for the CLIC vertex detector and gives an overview of recent R&D achievements in the domains of sensors, readout and detector integration.

CLIC vertex detector R&D

In order to achieve its primary objectives of heavy-flavour tagging and tau lepton identification, the CLIC vertex detector must precisely reconstruct displaced vertices. This requires accurate determination of the impact parameter and charge of tracks originating from the secondary vertex. Excellent spatial resolution must therefore be provided down to low polar angles, whilst maintaining low occupancy, low mass and low power dissipation. These requirements challenge current technological limits, and demand a broad programme of R&D. A detector concept is currently under development, comprising a hybrid pixel detector of small-pitch readout ASICs implemented in 65nm CMOS technology (CLICpix) combined with ultra-thin sensors. The readout chips are low-power, and power-pulsing is used to reduce further their power dissipation. This enables a forced gas cooling system in the vertex detector region. In this paper, the CLIC vertex detector requirements are reviewed and the current status of R&D on sensors, readout, powering, cooling and supports is presented.

Vertex-detector R&D for CLIC

A detector concept based on hybrid planar pixel-detector technology is under development for the CLIC vertex detector. It comprises fast, low-power and small-pitch readout ASICs implemented in 65 nm CMOS technology (CLICpix) coupled to ultra-thin sensors via low-mass interconnects. The power dissipation of the readout chips is reduced by means of power pulsing, allowing for a cooling system based on forced gas flow. In this paper the CLIC vertex-detector requirements are reviewed and the current status of R&D on sensors, readout and detector integration is presented.