Abstract
The vertex detector at the proposed CLIC multi-TeV linear e+e− collider must have minimal material content and high spatial resolution, combined with accurate time-stamping to cope with the expected high rate of beam-induced backgrounds. One of the options being considered is the use of active sensors implemented in a commercial high-voltage CMOS process, capacitively coupled to hybrid pixel ASICs. A prototype of such an assembly, using two custom designed chips (CCPDv3 as active sensor glued to a CLICpix readout chip), has been characterised both in the lab and in beam tests at the CERN SPS using 120GeV/c positively charged hadrons. Results of these characterisation studies are presented both for single and dual amplification stages in the active sensor, where efficiencies of greater than 99% have been achieved at −60V substrate bias, with a single hit resolution of 6.1μm. Pixel cross-coupling results are also presented, showing the sensitivity to placement precision and planarity of the glue layer.
Highlights
The demands for precision physics in combination with the challenging experimental conditions at the proposed electron-positron Compact LInear Collider (CLIC) have inspired a broad detector R&D program [1]
In the following we present first laboratory and test-beam measurement results for prototypes of an active High-Voltage Complementary Metal-Oxide-Semiconductor process (HV-CMOS) sensor (CCPDv3) capacitively coupled to a readout Application Specific Integrated Circuits (ASICs) (CLICpix)
The CCPDv3 is an ASIC implemented in a 180 nm high-voltage CMOS process, designed for use as an active sensor
Summary
The demands for precision physics in combination with the challenging experimental conditions at the proposed electron-positron Compact LInear Collider (CLIC) have inspired a broad detector R&D program [1]. The use of Capacitively Coupled Pixel Detectors (CCPD) has recently been proposed as an alternative [2]. In this approach active sensors with an amplification stage in each pixel are implemented in a commercial High-Voltage Complementary Metal-Oxide-Semiconductor process (HV-CMOS). The fast drift signal collected in this depleted layer is transformed to a voltage signal by a transimpedance amplifier and sent to a metal readout pad. This voltage signal is capacitively coupled through a thin (few microns) layer of glue to the corresponding input pixel pad of the readout ASIC. In the following we present first laboratory and test-beam measurement results for prototypes of an active HV-CMOS sensor (CCPDv3) capacitively coupled to a readout ASIC (CLICpix)
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