Abstract
The capacitive coupling between an active sensor and a readout ASIC has been considered in the framework of the CLIC vertex detector study. The CLICpix Capacitively Coupled Pixel Detector (C3PD) is a High-Voltage CMOS sensor chip produced in a commercial 180 nm HV-CMOS process for this purpose. The sensor was designed to be connected to the CLICpix2 readout chip. It therefore matches the dimensions of the readout chip, featuring a matrix of 128×128 square pixels with 25μm pitch. The sensor chip has been produced with the standard value for the substrate resistivity (∼20 Ωcm) and it has been characterised in standalone testing mode, before receiving and testing capacitively coupled assemblies. The standalone measurement results show a rise time of ∼20 ns for a power consumption of 5μW/pixel. Production of the C3PD HV-CMOS sensor chip with higher substrate resistivity wafers (∼20, 80, 200 and 1000 Ωcm) is foreseen. The expected benefits of the higher substrate resistivity will be studied using future assemblies with the readout chip.
Highlights
The concept of capacitive coupling between an active sensor and a readout ASIC has been considered in view of a system suitable for the vertex detector at the Compact Linear Collider (CLIC) [1].The vertex detector is the innermost active component of the CLIC detector, and given its location close to the interaction point, the requirements are highly demanding in terms of spatial resolution, material budget and power consumption
These requirements include a spatial resolution of ∼ 3 μm, a material budget of 0.2% X0 per detection layer and a power consumption limited to 50 mW/cm2
Before receiving assemblies with the CLICpix2 readout chip, a standalone characterisation was performed for the C3PD chip using a lab setup with bare C3PD chips wire-bonded on a PCB
Summary
The concept of capacitive coupling between an active sensor and a readout ASIC has been considered in view of a system suitable for the vertex detector at the Compact Linear Collider (CLIC) [1].The vertex detector is the innermost active component of the CLIC detector, and given its location close to the interaction point, the requirements are highly demanding in terms of spatial resolution, material budget and power consumption. A capacitance is formed between the coupling pads of the sensor and readout chips, allowing for the voltage pulse at the output of the HV-CMOS sensor to be detected and processed by the readout chip The benefit of this approach compared to a monolithic detector is that the digital circuitry can be decoupled from the sensor by means of placing all the (fast-switching) digital logic in the readout chip. Both the sensor and the readout chips are the successors of a first generation of chips that have been designed and tested in capacitively coupled assemblies in the framework of the CLIC vertex detector studies [6, 7]
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