Abstract
CLIC is a proposed linear e+e- collider designed to provide particle collisions at center-of-mass energies of up to 3 TeV. Precise measurements of the properties of the top quark and the Higgs boson, as well as searches for Beyond the Standard Model physics require a highly performant CLIC detector. In particular the vertex detector must provide a single point resolution of only a few micrometers while not exceeding the envisaged material budget of around 0.2% X0 per layer. Beam-beam interactions and beamstrahlung processes impose an additional requirement on the timestamping capabilities of the vertex detector of about 10 ns. These goals can only be met by using novel techniques in the sensor and ASIC design as well as in the detector construction.The R&D program for the CLIC vertex detector explores various technologies in order to meet these demands. The feasibility of planar sensors with a thickness of 50–150 μm, including different active edge designs, are evaluated using Timepix3 ASICs. First prototypes of the CLICpix readout ASIC, implemented in 65 nm CMOS technology and with a pixel size of 25×25μm 2, have been produced and tested in particle beams. An updated version of the ASIC with a larger pixel matrix and improved precision of the time-over-threshold and time-of-arrival measurements has been submitted. Different hybridization concepts have been developed for the interconnection between the sensor and readout ASIC, ranging from small-pitch bump bonding of planar sensors to capacitive coupling of active HV-CMOS sensors. Detector simulations based on Geant 4 and TCAD are compared with experimental results to assess and optimize the performance of the various designs.This contribution gives an overview of the R&D program undertaken for the CLIC vertex detector and presents performance measurements of the prototype detectors currently under investigation.
Highlights
CLICpix2 represents an advancement of this design with several improvements and a larger active area, and is currently under investigation in the laboratory
Several technologies are considered for planar silicon sensors
Active edge technology would allow the reduction of passive material by extending the active region of the sensor to the physical cutting edge
Summary
First prototype readout ASICs following the requirements of the CLIC vertex detector have been developed. The CLICpix ASIC design [6] is derived from the Timepix/Medipix chip family [7,8,9] and is implemented in a commercial 65 nm CMOS process with an active pixel array of 64 × 64. Each pixel features a charge sensitive amplifier (CSA), a discriminator as well as digital logic for the simultaneous measurement of a 4-bit time-of-arrival (ToA) and a 4-bit time-over-threshold (ToT) for every hit. The chip is operated in a shutter-based readout mode which is well-suited for the CLIC beam structure. It supports power pulsing of the analog circuitry and features an optional on-chip data compression. A first production of the CLICpix has been received and is currently being tested in the laboratory
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