Circuit Under Test Research Articles

Test Power Reduction through Reordering Algorithm Implementation and Advancements in BIST Architecture

Due to the reduction in transistor size, test engineers face a severe issue in power minimization. VLSI circuit's power dissipation has become a vital concern due to the switching activity of the Circuit Under Test (CUT). Switching activity is a significant factor in determining power consumption for CMOS VLSI circuits. In this paper, we formulate a distance estimation technique and reordering using the Tversky index. Here, the distance between the test vectors is calculated using the Tversky index with the formation of an adjacency matrix, and reordering is performed. The experimental results of the proposed method have been compared to different distance measures and existing techniques. It shows that the switching activity is reduced from 52.5% to 21.5%, and the average power reduction is from 42% to 14.6% when the distance is estimated on reordering using the Tversky index measure. Thus, the Tversky index distance measure performs better than the Hamming, gray, and Linear feedback shift register (LFSR) methods. Switching activity estimation for complex ISCAS circuits has been performed and compared with existing methods for superior performance. We have also developed a Built in Self-Test (BIST) for the C17 benchmark circuit, which uses the Tversky counter as a test pattern generator using the TANNER EDA tool. Thus, an efficient deterministic BIST for the C17 benchmark circuit was designed to detect all the stuck-at faults, and the same procedure can be used to create BIST for all CUT and precomputed test sets for real-time field testing.

SPI Master Slave Communication

The serial-peripheral interface (SPI) protocol also called asynchronous serial interface specification is used for communication between single master and single/multiple slaves. With the increase in number of slaves causing high complexity of circuit creates a demand in self-test ability feature for SPI module in order to test for fault free circuits. Built-In-Self-Test (BIST) in the answer for self-test in circuits as well as it helps in reduction of maintenance and testing cost. Design of BIST embedded SPI module with single master and single slave configuration has been introduced in these paper, Here 8-bit is transferred across the module, Where the Circuit under Test (CUT) is being Self-Tested with BIST feature for its correctness. This SPI module is designed using Verilog hardware description language(HDL) using EDA playground platform for application like applications specific integrated circuit (ASIC) or system on chip (SOC). SPI stands for the Serial Peripheral Interface. It is a serial communication protocol that is used to connect low-speed devices. It was developed by Motorola in the mid-1980 for inter-chip communication. It is commonly used for communication with flash memory, sensors, real-time clock (RTC), analog-to-digital converters, and more. It is a full-duplex synchronous serial communication, which means that data can be simultaneously transmitted from both directions. The main advantage of the SPI is to transfer the data without any interruption. Many bits can be sent or received at a time in this protocol. In this protocol, devices are communicated in the master-slave relationship. The master device controls the slave device, and the slave device takes the instruction from the master device. The simplest configuration of the Serial Peripheral Interface (SPI) is a combination of a single slave and a single master. But, one master device can control multiple slave devices

Automating the Generation of Programs Maximizing the Repeatable Constant Switching Activity in Microprocessor Units via MaxSAT

Throughout device testing, one key parameter to be considered is the switching activity (SWA) of the circuit under test (CUT). To avoid unwanted scenarios due to excessive power consumption during test, in most cases the SWA of the CUTs must be retained to a minimal value when the test stimulus is applied. However, there are specific cases where the opposite, namely the SWA maximization within the CUT, or a certain sub-module of it, can be proven beneficial. For example, during dynamic Burn-In testing we aim at maximizing the internal stress by applying suitable stimuli. This can be done in a functional manner by following the Software-Based Self-Test paradigm. However, generating such suitable programs represents a costly and arduous task for the test engineers. We consider the case where the CUT is a pipelined processor core and we aim to maximize the SWA of certain core sub-modules. We present a comprehensive methodology based on formal methods, able to automatically generate the best two-instruction stress-inducing sequence for the targeted processor module. The generated stimulus is composed of a short, arbitrarily-long repeatable sequence of a pair of assembly instructions, thus guaranteeing the maximum possible constant switching activity. The proposed method was applied to the OpenRISC 1200 and the RI5CY (PULP) processor cores demonstrating its effectiveness when compared to other methods. We show that the time for generating the best repeatable instruction sequence is limited in most cases, while the generated sequence can always achieve a significantly higher repeatable and constant SWA than other solutions.

An efficient method for faults diagnosis in analog circuits based on machine learning classifiers

The presented paper introduces an accurate approach for detecting and classifying parametric or soft faults that affect analog integrated circuits. This technique is based on the use of machine learning algorithm to improve the accuracy and the performance of fault classification process. To achieve this, the real and imaginary frequency responses of output voltage and supply current of the circuits under test (CUT) are used to extract features for both normal and faulty cases. These features are then exploited to train machine learning classifiers, from which the selected one among its equivalents is the quadratic discriminant classifier since it allowed the highest average accuracy score. The faults to be investigated are parametric ones affecting resistors and capacitors values. The proposed approach is validated using three filters circuits that are Sallen-Key band-pass filter, four op-amp biquad high-pass filter, and a leapfrog filter circuit. Obtained results indicate a high classification average accuracy for all circuits that are undergone testing. The proposed approach has provided a highest classification accuracy level comparing to other research works.

Fault Coverage Improvement of CMOS Analog Circuits Using Supply Current Testing Method

In this paper, a testing technique based on supply current verifying is presented, for fault detection of analog circuits containing CMOS operational amplifiers. This testing technique is employed and developed to maximize the fault coverage of the circuit under test (CUT) using transient and frequency responses of the supply current. This testing method is based on the over-sighting of the quiescent supply current (Iddq) of the CMOS operational amplifier operating in its quiescent mode and the supply current of the CMOS operational amplifier used as a Sallen-Key band pass filter in the AC and transient operating domains. The faults investigated in our study are of bridging and open circuit types that occur at the CMOS transistor level. The Pspice software was used for the CUT simulation by applying Monte-Carlo analysis in faulty and fault free conditions. Test parameters are extracted and selected to be used as input features of our classifier.

A Methodology for Accelerating FPGA Fault Injection Campaign Using ICAP

The increasing complexity of System-on-Chip (SoC) and the ongoing technology miniaturization on Integrated Circuit (IC) manufacturing processes makes modern SoCs more susceptible to Single-Event Effects (SEE) caused by radiation, even at sea level. To provide realistic estimates at a low cost, efficient analysis techniques capable of replicating SEEs are required. Among these methods, fault injection through emulation using Field-Programmable Gate Array (FPGA) enables campaigns to be run on a Circuit Under Test (CUT). This paper investigates the use of an FPGA architecture to speed up the execution of fault campaigns. As a result, a new methodology for mapping the CUT occupation on the FPGA is proposed, significantly reducing the total number of faults to be injected. In addition, a fault injection technique/flow is proposed to demonstrate the benefits of cutting-edge approaches. The presented technique emulates Single-Event Transient (SET) in all combinatorial elements of the CUT using the Internal Configuration Access Port (ICAP) of Xilinx FPGAs.

Automating the Generation of Programs Maximizing the Sustained Switching Activity in Microprocessor units via Evolutionary Techniques

During device testing, an important parameter to be considered by the test engineers is the switching activity (SWA) of the circuit under test (CUT). It is well known that the SWA must be kept to a minimum in order to avoid catastrophic scenarios on the CUTs, e.g., unacceptable peak power consumption or over-stressing that can lead to an artificial yield loss. However, there are scenarios, where the inverse, namely the switching activity maximization, can be proven beneficial. For example, this happens during Burn-In testing, when we aim at exercising the circuit under extreme operating conditions in terms of temperature and temperature gradients to accelerate aging phenomena in a controlled manner. In some cases, this is achieved by applying to the CUT stimuli in a functional manner, based on the Software-Based Self-Test (SBST) paradigm. Though, the generation of such appropriate programs for this task represents a challenge for the test engineers. In this paper we consider the scenario where the modules to be stressed are the units of a pipelined processor. We present a method, based on an evolutionary approach, that is able to automatically generate maximum stress programs, i.e., sequences of instructions achieving a high switching activity in the target module. With respect to other approaches, the generated sequences are built from the ground-up, are short and repeatable, thus guaranteeing their easy usability to stress a module (and increase its temperature). The processor we used for our experiments is the Open RISC 1200. Results demonstrate that the generated stimuli from the proposed method are effective in achieving a high value of sustained switching activity within the considered processor modules while also achieves a better results when comparing with other methods (e.g., stuck-at oriented test programs).

An Intelligent Sensing Framework for Post-Manufacturing Performance Measurement and Healing of CSVCO

With CMOS technology scaling for miniaturization and performance improvement, analog and radio frequency integrated circuits (RFICs) are very much affected by process variations leading to performance degradation. A post-manufacturing healing mechanism with low overhead is desirable to compensate for these variations. A machine learning (ML)-assisted sensing mechanism has been proposed in this work for design of nonintrusive process variation sensor (PVS). Low-cost test signatures (TSs) extracted from these PVS are placed close to the circuit under test (CUT) and this does not load or couple to any nodes of CUT. As the TSs remain invariant with the shifts in control knobs (CKs), performance healing against process variations can be achieved with a single set of extracted TSs. A novel one-step healing approach is proposed in this work for selection of appropriate CK with the help of a neural regression model during the production test in automated test equipment (ATE). The proposed healing approach is illustrated on a current-starved voltage-controlled oscillator (CSVCO) circuit, to recover yield loss due to fabrication process variations.

On-chip test vector generation and downsampling for testing RSFQ circuits

An on-chip high-frequency testing method for rapid single flux quantum circuits is proposed. This method employs test vectors based on pseudo-random sequences created by an on-chip high-frequency clock generator (CG) and a linear feedback shift register with parallel outputs (LSPO). Downsamplers (DSMs) at the outputs of a circuit under test (CUT) decimate the CUT output data so that high-frequency testing can be performed at sufficiently low data rates between the CUT and room-temperature electronics. The proposed testing can continuously test the circuit at high frequency with low-cost instruments. All of the critical subsystems, including LSPO, CG, and DSM, were designed, fabricated, and successfully tested. We validated proper operation at up to 40 GHz, confirming the concept and execution.

Adaptive BIST for Concurrent On-Line Testing on Combinational Circuits

Safety-critical systems embedding concurrent on-line testing techniques are vulnerable to design issues causing the degradation of totally self-checking (TSC) property, which is proved to be fatal for further operations (e.g., space electronics, medical devices). In addition to the exploration of the degradation of TSC property over time, a concurrent on-line testing architecture is offered that adjusts the input activity, addressing the absence of input values or the low frequency of their appearance (e.g., during sleep mode). During concurrent on-line testing, the inputs of the circuit under test (CUT) are, at the same time, its test vectors. This architecture tolerates possible degradation of the terms that contribute to the calculation of the totally self-checking goal (TSCG(t)). An adaptive built-in self-test (BIST) unit is proposed that dynamically applies test vector subsets when permitted, based on the frequency of appearance of the input values. The clustering of the inputs is based on the k-means algorithm and, in combination with the ordering of the test vectors to minimize the subsets, results in partitioning the test procedure in a significantly shorter time. The comparison to other solutions used for concurrent on-line testing showed that the proposed adaptive BIST has significant advantages. It can cope with rare occurrences, or even no occurrence, of input values by enabling the BIST mechanism appropriately. The results showed that it may increase the TSCG(t) up to almost 90% when applied during a low-power mode and present better concurrent test latency (CTL) when assumptions regarding the availability of all input values and the probability of occurrence are not realistic.

A Novel Fault Diagnosis Method for Analog Circuits Based on Multi-Input Deep Residual Networks with an Improved Empirical Wavelet Transform

Analog circuits play an essential role in electronic systems. To strengthen the reliability of sophisticated electronic circuits, this paper proposes a novel analog circuit fault diagnosis method. Compared with traditional fault diagnosis, the fault diagnosis process in this paper uses a square wave as the stimulus of the circuit under test (CUT), which is beneficial for obtaining the response of the CUT with rich time and frequency domain information. The improved empirical wavelet transform (EWT), which can more accurately extract the amplitude modulated–frequency modulated (AM-FM) components, is used to preprocess the original response. Finally, based on the preprocessed data, a multi-input deep residual network (ResNet) is constructed for fault feature extraction and fault classification. The multi-input ResNet is a powerful approach for learning the fault characteristics of the CUT under different faults by learning the characteristics of the AM-FM components. The effectiveness of the method proposed in this paper is verified by comparing different fault diagnosis methods.

A BIST Scheme for Bootstrapped Switches

This paper proposes a built-in self-test (BIST) scheme for detecting catastrophic faults in bootstrapped switches. The clock signal and the gate voltage of the sampling MOS transistor are taken as the observation signals in the proposed BIST scheme. Usually, the gate voltage of the sampling MOS transistor is greater than or equal to the supply voltage when the switch is turn on, and such a voltage is not suitable for observation. To solve this problem, a low power supply voltage is provided for the bootstrapped switch to obtain a suitable observation voltage. The proposed BIST scheme and the circuit under test (CUT) are realized with transistor level. The proposed BIST scheme was simulated by HSPICE. The simulated fault coverage is approximately 87.9% with 66 test circuits.

Synchronized Multi-Rate Test Pattern Generation Using Hybrid Twisted Ring Counter and LFSR for BIST Application

This work presents a new approach for built-in test pattern generation (BIST) based on the variable rate clock-driven linear feedback shift register (LFSR) and twisted-ring counters (TRCs). The proposed technique operates on different operating clocks for generating deterministic test pattern sequence for the circuit under test (CUT). The test vectors generated by LFSR are transformed and reproduced with TRC results. The TRC design constitutes of only flip-flops, which be used as a potential alternative to improved seed storage and complex multi polynomial configurations in LFSR.Moreover, the control logic is simplified with synchronized multi-rate clock generation and can be easily extended for any test cubes among multiple CUTs. The randomness characteristics of LFSR are retained with improved memory efficiency and considerable complexity reduction. Experimental results validate the proposed test pattern generator (TPG) over existing well-known LFSRs models, and its randomness is proved with ISCAS benchmark circuits.

A Neural Network Classifier with Multi-Valued Neurons for Analog Circuit Fault Diagnosis

In this paper, we present a new method designed to recognize single parametric faults in analog circuits. The technique follows a rigorous approach constituted by three sequential steps: calculating the testability and extracting the ambiguity groups of the circuit under test (CUT); localizing the failure and putting it in the correct fault class (FC) via multi-frequency measurements or simulations; and (optional) estimating the value of the faulty component. The fabrication tolerances of the healthy components are taken into account in every step of the procedure. The work combines machine learning techniques, used for classification and approximation, with testability analysis procedures for analog circuits.

Fault Diagnosis of Linear Analog Electronic Circuit Based on Natural Response Specification using K-NN Algorithm

This paper reports a novel method for parametric fault diagnosis in linear analog electronic circuits using distance weighted cosine K-Nearest Neighbours (K-NN) algorithm that performs data classification on the basis of cosine similarity between data features or attributes. In this approach the analog electronic Circuit Under Test (CUT) is represented in the form of a transfer function model and natural response specifications of the system such as damping ratio, natural frequency and static gain of the system are extracted as features from this model. For experimentation purpose a second order Sallen-Key band pass filter and a fourth order Chebychev Type 1 low pass filter is considered, the corresponding fault classes are created for each of the circuit. The parameter values of the passive components in the system have been varied to derive the features, and each component whose tolerance varied is labelled with a corresponding fault class. The proposed methodology classifies faulty classes with accuracy greater than 95%.

On-Chip Thermal Profiling to Detect Malicious Activity: System-Level Concepts and Design of Key Building Blocks

This article introduces an on-chip anomaly monitoring system design approach that is based on thermal profiling and side-channel analysis. The strategy aims at the realization of nonintrusive hardware Trojan (HT) detection over the lifetime of the circuit under test (CUT). To evaluate the capability of the proposed HT detection system, the on-chip electrothermal coupling is modeled as part of the simulation technique, which associates local thermal activities with circuit-level power consumption using a standard electrical simulator. To monitor the thermal profiles on chips with high sensitivity to local temperature changes and the resilience to flicker noise, the sensor architecture described in this article is the first differential temperature sensor equipped with a chopping mechanism. A methodology is described to utilize principal component analysis (PCA) to extract critical information from the quantized output of the system for effective HT detection in the presence of noise. The complete sensor signal path of the system was designed and simulated with foundry-supplied device models (130-nm CMOS technology), and the impact due to process variations have been considered via Monte Carlo simulations. The results indicate that small Trojans with approximately 2 μW of power can be detected within the thermal profile of a CUT consuming more than 500 μW. As the first step to prove the feasibility of on-chip quantization in the HT detection system, a prototype 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) was fabricated with 130-nm CMOS technology.

Simple Circuits Recognize Parametric Blames in Multi-Input Simple Circuits

The point of this paper is to recognize parametric blames in multi-input simple circuits by addressing for the coefficients of a polynomial relapse model utilizing conventional direct least squares strategies, with some consideration applied in the arrangement. The multi-input circuit yield is communicated as far as more than one info factors utilizing polynomial coefficients. In the proposed approach, the worth of every part of the circuit under test (CUT) is differed inside its resistance limit utilizing Monte-Carlo reproduction to figure its deficiency free polynomial coefficient limits. The CUT is then proclaimed flaw free or broken dependent on the aftereffect of the examination of its assessed polynomial coefficients with the issue free coefficients. As far as we could possibly know, parametric flaw recognition in multi-input simple circuits utilizing polynomial relapse demonstrating is endeavored without precedent for the writing. The adequacy of the proposed strategy is exhibited by means of two contextual investigations, in particular, a lead slack circuit and the PI compensator of a pinnacle current-modecontrolled buck-type exchanging converter.

Innovative Transient Study of Tri-Bandpass Negative Group Delay Applied to Microstrip Barcode-Circuit

A transient study of bandpass (BP) negative group delay (NGD) function is devoted in this paper. The transient analysis is applied to an original topology of NGD barcode-shape microstrip circuit. The performed investigation explains how to realize the transient analysis of tri-band NGD circuit. The time-domain (TD) parametrization of the test is established from the BP-NGD specifications of the circuit under test (CUT) based on the S-parameter model. The input signal is a Gaussian pulse characterized in function of the NGD bandwidth (BW) and center frequency. The feasibility of the BP-NGD transient study is illustrated with experimentation based on ultra-wide band (UWB) pulse generator. As proof-of-concept, barcode NGD circuit exhibiting tri-band NGD value-center frequency-bandwidth, (−5.9 ns, 2.128 GHz, 20 MHz), (−7.4 ns, 2.3 GHz, 14 MHz) and (−4.8 ns, 2.42 GHz, 14 MHz) has been fabricated and tested. The transient simulations and experiences confirm that the output signal envelopes of the barcode NGD prototype present leading and tailing edges in time-advance of input ones when the carrier frequency is set equal to the NGD center frequency.

A Statistical Approach of Analog Circuit Fault Detection Utilizing Kolmogorov–Smirnov Test Method

This work presents a testing technique based on ‘Kolmogorov–Smirnov’ (K–S) test for detection of parametric faults in analog circuits. The proposed method is a time-domain signal processing technique that compares the statistical similarity in terms of ‘Empirical Cumulative Distribution Function’ (ECDF) of the outputs of the circuit when the input of the circuit is a random analog signal. ‘Multivariate Adaptive Regression Splines’ (MARS) technique is used to map the tolerances of functional metrics to the components of the circuit under test (CUT). Two benchmark circuits, i.e., second-order Sallen–Key band-pass filter and weakly nonlinear cascade amplifier are tested to validate the proposed fault detection technique. The proposed statistical approach with the use of random analog signal as input excitation results reduction of complexity for designing input test signal and increases fault coverage in the analog circuit testing. The proposed method is testified experimentally for Sallen–Key band-pass filter. The experimental results are in good agreement with the simulated results.

Analog Circuit Faulty Parameter Identification Based on Two-Objective Evolutionary Algorithm

Faulty parameter identification is vital to prediction of remaining useful life of circuit under test (CUT). Based on the transfer function, we use measured faulty response to deduce the possible faulty parameters. It is known that the measured response of the CUT is the function of the analog parameters. Usually, the number of independent response is much less than that of the analog component. The underdetermined equations have infinite solutions. In other words, there are lots of combinations of analog parameters that can generate the same faulty response. Hence, it is more valuable to deduce the possible faulty parameter range than to estimate a single faulty parameter. The deduction is accomplished by using a modified two-objective genetic algorithm. The individual that minimizes the deviation, viz., difference between the simulated and measured faulty responses, gives the possible faulty parameter. Finding the possible faulty parameter range equals to finding the minimal and maximal faulty parameters that can zero the deviation. Hence, we have to simultaneously minimize (and maximize) the faulty parameters and minimize the deviation. It is transformed into a two-objective optimization problem. We use Pareto dominated method to minimize and maximize the faulty parameter. The effectiveness of the proposed method is examined by using filter circuit examples.