Abstract
In this paper, we present a new method designed to recognize single parametric faults in analog circuits. The technique follows a rigorous approach constituted by three sequential steps: calculating the testability and extracting the ambiguity groups of the circuit under test (CUT); localizing the failure and putting it in the correct fault class (FC) via multi-frequency measurements or simulations; and (optional) estimating the value of the faulty component. The fabrication tolerances of the healthy components are taken into account in every step of the procedure. The work combines machine learning techniques, used for classification and approximation, with testability analysis procedures for analog circuits.
Highlights
The fault diagnosis problem of analog circuits can be considered to be far from a definitive solution, even if in the last years a large amount of research has been dedicated to it (e.g., [1,2,3,4,5,6,7,8,9,10,11,12])
The third advantage is the ability of Multilayer Neural Network with Multi-Valued Neurons (MLMVN) to employ a batch learning algorithm [30,34], which adjusts the weights not moving from one learning sample to another, but for the entire learning set after the errors were calculated for all learning samples
In the case of second order Canonic ambiguity group (CAG), it is not possible to uniquely identify the failure of the components belonging to these groups; this means that all the components not belonging to CAGs of order 2 are identifiable and each of them is a fault class (FC), while, for the components belonging to CAGs of order 2, there are two cases [22,39]: N, and, it is useful to extract the “ambiguity groups” of the circuit under test (CUT)
Summary
The fault diagnosis problem of analog circuits can be considered to be far from a definitive solution, even if in the last years a large amount of research has been dedicated to it (e.g., [1,2,3,4,5,6,7,8,9,10,11,12]). Further examples of the strategic role of testability analysis are the recently proposed analog fault diagnosis methods under the single-input single-output single-fault scenario [8,9] They are quite interesting because they do not require the knowledge of the analytic expression of the network functions and are, in turn, predicated on a fault model in the form of a geometric locus in the complex plane. The possibility to vary the faulty parameters over a large range is an important characteristic not present in the most part of fault diagnosis literature It should be taken into account that the “single fault” hypothesis adopted in this work was relevant in the analytical development of the proposed method, but was definitely the most interesting in the family of applications considered in this paper.
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