Circuit Noise Research Articles

High resolution atomic force microscopy with an active piezoelectric microcantilever.

Active microcantilevers with on-chip sensing and actuation provide significant advantages in tapping mode Atomic Force Microscopy (AFM). Collocated transduction allows for effective manipulation of cantilever dynamics through feedback control, enabling higher scan rates. However, the adjacency of the sensing and actuation electrodes is known to result in a high level of feedthrough, leading to a low imaging resolution. Readout circuit noise further deteriorates the imaging precision. Here, we investigate the noise sources that affect AFM microcantilevers with collocated aluminum nitride (AlN) actuator-sensor pairs. We reported these cantilevers in earlier work and demonstrated that they display a very low level of feedthrough between the actuation and sensing electrodes. We present a high signal-to-noise ratio (SNR) sensing method that enables us to demonstrate high-resolution AFM on a calibration grating with nm-step silicon carbide (SiC) terraces. Measuring the Lorentzian response of the cantilever's Brownian motion with the on-chip active sensor at resonance enables us to calibrate the dynamic stiffness at the first fundamental resonance mode, without utilizing an optical sensor.

IDENTIFICATION OF WHITE NOISE AND 1/f IN CURRENT MIRROR CONFIGURATION BASED ON VDS MOSFET

Identifying noise in the Current Mirror (CM) circuit is essential to locate noise signals in biosensor applications so that measurements become more accurate and precise. There are two dominant types of noise: white noise, which consists of thermal noise and shot noise, and also low-frequency noise (1/f noise). The main component of the CM circuit is the BS250 type MOSFET, which works by varying the width of the charge carrier channelcontrolled by the voltage at the gate. When the drain is given a voltage, electrons will flow from the source to the drain which generates the noise.This study was carried out to identify the noise in the CM configuration by varying the reference voltage of MOSFET using the PCI-6221 card data integrated with the LabVIEW program. The reference voltage values ​​used are 1 mV, 10 mV, and 100 mV to determine the effect of the input voltage on the CM circuit noise signal, while the measurement frequency is varied from 0.1 Hz to 100 kHz with a resolution of 0.1 Hz. The results show that the noise characteristics vary with the applied voltage, which will increase at a higher voltage. Analysis of 1/f noise at frequencies up to 0.2 Hz has a gradient increase of up to 10 times for each given voltage value. Based on the value of the data distribution on the white noise measurement, it shows that a voltage of 100 mV produces the highest noise with an average of 3.62 × 10-7 Vrms/Hz1/2. The results of this study are used in the design of CM circuits with minimal noise.

The Design of a Low Noise and Low Power Current Readout Circuit for Sub-pA Current Detection Based on Charge Distribution Model

In this article, we proposed an analytical model based on charge distribution for switched-capacitor trans-impedance amplifiers (SCTIAs). The changes in the load state of the amplifier under different operating conditions and the influence of the gain of the operational amplifier (Opamp) on the trans-impedance gain are analyzed to improve the design theory of switched-capacitor trans-impedance amplifiers. According to the conclusion drawn from the analysis, the trans-impedance amplifier (TIA) has been designed by adopting “correlated double sampling technology” and “cross-connection technology” to optimize input-referred noise current, power consumption, and trans-impedance gain. As a result, the trans-impedance gain reaches up to 206 dB, while the bandwidth is 3 kHz. The current readout system achieves an input-referred noise current floor of 2.96 fA/Hz at 1 kHz, and the power consumption of the system is 0.643 mW. The circuit has been simulated with the technology of 0.18 μm, and the layout area is 1000 μm × 500 μm.

Mitigating errors by quantum verification and postselection

Correcting errors due to noise in quantum circuits run on current and near-term quantum hardware is essential for any convincing demonstration of quantum advantage. Indeed, in many cases it has been shown that noise renders quantum circuits efficiently classically simulable, thereby destroying any quantum advantage potentially offered by an ideal (noiseless) implementation of these circuits. Although the technique of quantum error correction (QEC) allows correcting these errors very accurately, QEC usually requires a large overhead of physical qubits which is not reachable with currently available quantum hardware. This has been the motivation behind the field of quantum error mitigation, which aims at developing techniques to correct an important part of the errors in quantum circuits, while also being compatible with current and near-term quantum hardware. In this work, we present a technique for quantum error mitigation which is based on a technique from quantum verification, the so-called accreditation protocol, together with postselection. Our technique allows for correcting the expectation value of an observable $O$, which is the output of multiple runs of noisy quantum circuits, where the noise in these circuits is at the level of preparations, gates, and measurements. We discuss the sample complexity of our procedure and provide rigorous guarantees of errors being mitigated under some realistic assumptions on the noise. Our technique is tailored to time-dependent behaviors, as we allow for the output states to be different between different runs of the accreditation protocol. We validate our findings by running our technique on currently available quantum hardware.

Noise-assisted variational quantum thermalization

Preparing thermal states on a quantum computer can have a variety of applications, from simulating many-body quantum systems to training machine learning models. Variational circuits have been proposed for this task on near-term quantum computers, but several challenges remain, such as finding a scalable cost-function, avoiding the need of purification, and mitigating noise effects. We propose a new algorithm for thermal state preparation that tackles those three challenges by exploiting the noise of quantum circuits. We consider a variational architecture containing a depolarizing channel after each unitary layer, with the ability to directly control the level of noise. We derive a closed-form approximation for the free-energy of such circuit and use it as a cost function for our variational algorithm. By evaluating our method on a variety of Hamiltonians and system sizes, we find several systems for which the thermal state can be approximated with a high fidelity. However, we also show that the ability for our algorithm to learn the thermal state strongly depends on the temperature: while a high fidelity can be obtained for high and low temperatures, we identify a specific range for which the problem becomes more challenging. We hope that this first study on noise-assisted thermal state preparation will inspire future research on exploiting noise in variational algorithms.

Analysis of Noise in Current Mirror Circuits Based on CNTFET and MOSFET

In this paper we present a comparative analysis of noise performance of Carbon Nanotube Field Effect Transistors (CNTFETs) and MOSFET, through the design of two circuits: a basic current mirror and self-bias current mirror, each time with different current values. For this aim we use a semi-empirical compact CNTFET model, already proposed by us, including noise source contributions, and the BSIM4 model for MOS device. Then we analyze and discuss the spectral density of output noise current, comparing the two considered technology. The software used is Advanced Design System (ADS), compatible with the Verilog A programming language.

A method to reduce excitation circuit noise of fluxgate sensor

This paper designs a three-axis closed-loop fluxgate system for geophysical prospecting, which contains excitation, induction, and feedback circuits. By analyzing and comparing the noise levels before and after the system operation, it is concluded that the main factor affecting the fluxgate performance is the excitation circuit noise. By analyzing the principle of fluxgate, the noise on the induction signal and feedback signal can reduce the accuracy of fluxgate and even lead to system instability in serious cases. In this paper, a passive filter circuit is designed to reduce the noise associated with the fundamental frequency from the source to ensure stable operation and improved performance of the system. Simulation and experimental data show that after using the filter circuit, the secondary frequency noise level of the induction signal and the feedback signal noise level are reduced by 10 times, and the trend capturing capability under external magnetic field is greatly improved.

The Charge-Based Flicker Noise Model for HEMTs

The flicker noise modeling is of great significance in many applications of high electron mobility transistors (HEMTs) in low noise circuits. In this letter, a novel charge-based flicker noise model for HEMTs is proposed, which introduces the trap-charge fluctuation-based flicker noise modeling method to the charge-based MIT virtual source (MVS) HEMT model. This model is highly compatible with the MVS HEMT model. It can predict the flicker noise performance in a physically rigorous and accurate way. This model is verified by the excellent agreement between simulations and measurement results.

Research on the Denoising Method of Intelligent Ultrasonic Fuel Consumption Testing in Automobiles

Using ultrasonic time difference method to test automobile fuel consumption, the test accuracy mainly depends on the testing system timing accuracy and ultrasonic flow sensor output signal-to-noise ratio. At present, the timing accuracy of the single-chip can reach the level of picosecond, and the noise mixed in the output signal of the ultrasonic converter is the main factor affecting the accuracy of fuel consumption testing. When the receiving signal contains noise, it will cause the signal amplitude to fluctuate, making the measurement time error. The analysis of same-frequency noise, circuit noise and colored noise is carried out, and the feasible measures to eliminate noise are put forward to provide reference for accurate calculation of sound and development of high-precision automobile fuel consumption test instruments.

Model Implementation of Lorentzian Spectra for Circuit Noise Simulations in the Frequency Domain

This work presents a new method for the Verilog-A implementation of Lorentzian noise models, in a module called VERILOR, which can automatically generate either Lorentzian or 1/f-like noise spectra depending on the trap density and gate oxide area, for all bias conditions, in a one-step simulation. Based on statistical experimental data, we demonstrate the importance of Lorentzian noise modeling in contrast to classic frequency domain 1/f or time domain Random Telegraph Noise (RTN) modeling, in terms of PSD, total noise power, and device-to-device noise variability reproduction. Moreover, we validate the applicability of VERILOR in circuit simulators in both frequency and time domain, and how it can enable precise noise variability studies at a circuit level. Finally, fundamental digital and analog circuits such as the Ring Oscillator are used to showcase the usefulness and applicability of the VERILOR model in circuit noise simulations.

Phase demodulation of fiber vibration sensing by modified ellipse fitting algorithm based on local outlier factor optimization

In the existing ellipse fitting algorithms, the Lissajous figure is used to solve the demodulation error caused by the non-ideal 3×3 couplers. However, the influence of circuit noise and phase noise on Lissajous figure are not fully considered in the studies. In this work, an ellipse fitting demodulation method based on local outlier factor (LOF) algorithm is proposed, which can effectively eliminate the outlier points in Lissajous figure caused by noises. The proposed method proves to achieve the accurate demodulation of the signals by numerical simulations. In addition, the Monte Carlo analysis is used to obtain the comprehensive error rate of about 0.13%, which verifies the stability of the proposed method. Compared with the traditional least square fitting method, this method improves the stability and accuracy of demodulated signals.

Accelerated Quantum Monte Carlo with Mitigated Error on Noisy Quantum Computer

Quantum Monte Carlo and quantum simulation are both important tools for understanding quantum many-body systems. As a classical algorithm, quantum Monte Carlo suffers from the sign problem, preventing its application to most fermion systems and real time dynamics. In this paper, we introduce a novel non-variational algorithm using quantum simulation as a subroutine to accelerate quantum Monte Carlo by easing the sign problem. The quantum subroutine can be implemented with shallow circuits and, by incorporating error mitigation, can reduce the Monte Carlo variance by several orders of magnitude even when the circuit noise is significant. As such, the proposed quantum algorithm is applicable to near-term noisy quantum hardware.

Mitigating Depolarizing Noise on Quantum Computers with Noise-Estimation Circuits.

A significant problem for current quantum computers is noise. While there are many distinct noise channels, the depolarizing noise model often appropriately describes average noise for large circuits involving many qubits and gates. We present a method to mitigate the depolarizing noise by first estimating its rate with a noise-estimation circuit and then correcting the output of the target circuit using the estimated rate. The method is experimentally validated on a simulation of the Heisenberg model. We find that our approach in combination with readout-error correction, randomized compiling, and zero-noise extrapolation produces close to exact results even for circuits containing hundreds of CNOT gates. We also show analytically that zero-noise extrapolation is improved when it is applied to the output of our method.

Error Mitigation for Universal Gates on Encoded Qubits.

The Eastin-Knill theorem states that no quantum error-correcting code can have a universal set of transversal gates. For Calderbank-Shor-Steane codes that can implement Clifford gates transversally, it suffices to provide one additional non-Clifford gate, such as the T gate, to achieve universality. Common methods to implement fault-tolerant T gates, e.g., magic state distillation, generate a significant hardware overhead that will likely prevent their practical usage in the near-term future. Recently, methods have been developed to mitigate the effect of noise in shallow quantum circuits that are not protected by error correction. Error mitigation methods require no additional hardware resources but suffer from a bad asymptotic scaling and apply only to a restricted class of quantum algorithms. In this Letter, we combine both approaches and show how to implement encoded Clifford+T circuits where Clifford gates are protected from noise by error correction while errors introduced by noisy encoded T gates are mitigated using the quasiprobability method. As a result, Clifford+T circuits with a number of T gates inversely proportional to the physical noise rate can be implemented on small error-corrected devices without magic state distillation. We argue that such circuits can be out of reach for state-of-the-art classical simulation algorithms.

A high-bandwidth low current transimpedance amplification circuit

A measuring circuit is designed based on the transimpedance amplifier. The methods of reducing parasitic capacitance and improving amplifier performance are introduced in detail. The influence of the parasitic capacitance generated by the feedback resistors on the bandwidth in the transimpedance amplification circuit is discussed. The circuit can measure the wide-dynamic-range low current ranging from 10-13 A to 10-5 A in four ranges. The circuit's bandwidth is up to 500 Hz when the circuit can normally work to measure a wide-range low current. The peak-to-peak amplitude of circuit noise is less than 0.22 pA. The current drift is less than 1.06 fA/∘C over a temperature range of 0∘C to 85∘C, and the integral nonlinearity is less than 0.25%.

Development of a High Performance 1280×1024 InGaAs SWIR FPA Detector at Room Temperature

A 1280 × 1,024 In0.53Ga0.47As short wave infrared (SWIR) focal plane array (FPA) detector with a planar-type back-illuminated process has been fabricated. With indium bump flip-chip bonding techniques, the InGaAs photodiode arrays were hybrid-integrated to the CMOS readout integrated circuit (ROIC) with correlated double sampling (CDS). The response spectrum is 0.9–1.7 μm. The test results show that the dark current density is 2.25 nA/cm2 at 25 °C, the detectivity D* is up to 1.1 × 1013 cm · Hz1/2/W, the noise electron is as low as 48 e− under correlated double sampling mode, the quantum efficiency is 88% at 1550 nm, and the operability is more than 99.9%. Moreover, the dark current and noise electron have been studied theoretically in depth. The results indicate that the diffusion current is the main contribution of the dark current, and the readout integrated circuit noise electron is the main source of FPA noise.

Understanding and compensating for noise on IBM quantum computers

Quantum algorithms offer efficient solutions to computational problems that are expensive to solve classically. Publicly available quantum computers, such as those provided by IBM, can now be used to run small quantum circuits that execute quantum algorithms. However, these quantum computers are highly prone to noise. Here, we introduce important concepts of quantum circuit noise and connectivity that must be addressed to obtain reliable results on quantum computers. We utilize several examples to show how noise scales with circuit depth. We present Simon's algorithm, a quantum algorithm for solving a computational problem of the same name, explain how to implement it in IBM's Qiskit platform, and compare the results of running it both on a noiseless simulator and on physical hardware subject to noise. We discuss the impact of Qiskit's transpiler, which adapts ideal quantum circuits for physical hardware with limited connectivity between qubits. We show that even circuits of only a few qubits can have their success rate significantly reduced by quantum noise unless specific measures are taken to minimize its impact.

An improved transistor noise equivalent circuit model for silicon‐on‐insulator transistors considering the frequency dispersion effect

AbstractIn this paper, an improved transistor equivalent circuit noise model is proposed. This model takes the frequency dispersion effects into account and modified the induced gate current source (Ig) equation based on the classical Van der Ziel noise model. First, the conductance at Vd = 0 V (gd0) is derived from DC bias condition, and the accuracy of channel thermal noise (Id) is verified. Then, by analyzing the physical structure of the silicon‐on‐insulator (SOI) transistor, an equivalent lumped‐parameter circuit model is established. The element initial values are extracted based on the measured S‐parameters. Then, the parameters in the Ig equation are obtained through noise circle simulation in comparison with measurement data. In contrast to existing models, the frequency dispersion effect is analyzed and modeled using a three‐order polynomial. The results show that with respect to the traditional noise model, the noise circle's root‐mean‐square error of this work is decreased from 23.16 to 1.55.

A Novel Method to Control Leakage and Noise in Domino Circuit for Wide Fan-In OR Logic

This paper proposes a novel method to control leakage and noise in domino circuits for wide fan-in OR logic with low power consumption, low process variation, and higher noise margin under the similar delay condition. In the proposed method, output and dynamic nodes are isolated from the PDN (Pull-Down Network) to improve the noise immunity and reduce switching activity. Further, with the aid of a transistor in the stack, the sub-threshold current is reduced. Thus, the proposed domino is applicable for high-speed and low-power applications in deep sub-micro-range. Simulation results show that the proposed domino improves the noise immunity and figure of merit (FOM) by factors of 1.95 and 2.34, respectively, with respect to the conventional domino with a footer. Along with this improvement, 26% reduction is also observed in power consumption. The entire simulations for all the domino circuits are done at 45-nm CMOS technology by using SPECTRE simulator under the Cadence Virtuoso environment.

Practical Quantum Error Correction with the XZZX Code and Kerr-Cat Qubits

The development of robust architectures capable of large-scale fault-tolerant quantum computation should consider both their quantum error-correcting codes, and the underlying physical qubits upon which they are built, in tandem. Following this design principle we demonstrate remarkable error correction performance by concatenating the XZZX surface code with Kerr-cat qubits. We contrast several variants of fault-tolerant systems undergoing different circuit noise models that reflect the physics of Kerr-cat qubits. Our simulations show that our system is scalable below a threshold gate infidelity of $p_\mathrm{CX} \sim 6.5\%$ within a physically reasonable parameter regime, where $p_\mathrm{CX}$ is the infidelity of the noisiest gate of our system; the controlled-not gate. This threshold can be reached in a superconducting circuit architecture with a Kerr-nonlinearity of $10$MHz, a $\sim 6.25$ photon cat qubit, single-photon lifetime of $\gtrsim 64\mu$s, and thermal photon population $\lesssim 8\%$. Such parameters are routinely achieved in superconducting circuits.