Chip Performance Research Articles

Dopant concentrations analysis on electro-optic performances of gallium nitride-based ultraviolet light-emitting diode chip

Dopant concentrations analysis on electro-optic performances of gallium nitride-based ultraviolet light-emitting diode chip

Environmental sustainability by a comprehensive environmental and energy comparison analysis in a wood chip and rice straw biomass-fueled multi-generation energy system

Biomass-based energy systems are gaining popularity as a clean and renewable source of energy, and have the potential to be a major contributor to the transition towards a sustainable energy future. In this regard, a novel multi-generation energy system is developed based on the biomass combustion. Wood chip and rice straw biomass is combusted with air agent and triggers an integrated system comprises a gas turbine cycle, a proton exchange membrane electrolyzer, a supercritical carbon dioxide Brayton cycle, and a humidification-dehumidification desalination system. The performances of wood chip and rice straw in triggering the system are compared from environmental and energy indicators viewpoints. The system fueled by wood chip emits lower carbon dioxide emission compared to the system fueled by rice straw (8.294 g/kWh compared to 10.41 g/kWh). However, the rice straw-fueled system results in higher efficiency than the wood chip-fueled system (69.9% compared to 69.1%). The system fueled by wood chip produces 2.68 kg/h of hydrogen while this value if 1.96 kg/h for the system fueled by rice straw. The research validated the possibility of utilizing energy systems that incorporate wood chip and rice straw biomass across various generations and showed the superiority of the wood chip in most cases.

A capillary-based microfluidic chip with the merits of low cost and easy fabrication for the rapid detection of acute myocardial infarction

Point-of-care testing methods currently utilize rapid, portable, inexpensive, and multiplexed on-site detection. Microfluidic chips have become a very promising platform with broad development prospects due to their breakthrough improvement in miniaturization and integration. However, the conventional microfluidic chips still have disadvantages, such as difficulty in fabrication processing, long production time and high cost, which hinder its applications in the fields of POCT and in vitro diagnostics. In this study, a capillary-based microfluidic chip with the characteristics of low cost and easy fabrication was developed for the rapid detection of acute myocardial infarction (AMI). Several short capillaries, which were already conjugated with the capture antibodies respectively, were connected by peristaltic pump tubes and then formed the working capillary. Two working capillaries were encapsulated in the plastic shell and ready for the immunoassay. Multiplex detection of Myoglobin (Myo), cardiac troponin I (cTnI) and creatine kinase-MB (CK-MB) were chosen to demonstrate the feasibility and analytical performance of the microfluidic chip, which requires rapid and accurate detection during diagnosis and therapy for AMI. The capillary-based microfluidic chip required tens of minutes to prepared, and its cost was less than $1. The limit of detection (LOD) was 0.5 ng/mL for Myo, 0.1 ng/mL for cTnI and 0.5 ng/mL for CK-MB respectively. The capillary-based microfluidic chips with easy fabrication and low cost hold promise for the portable and low-cost detection of target biomarkers.

Reconfigurable linear feedback shift register for wireless communication and coding

<p>Linear feedback shift register (LFSR) is the basic building block of the communication system used in different coding, error detection and correction codes, such as gold, low-density parity check (LDPC), polar, and turbo codes. There are simple shift register-based n-bit counters with a few XOR gates that behave pseudo-randomly. The LFSR is used in chip hardware for high-speed operations, error control, and the generation of pseudo-random numbers. The hardware chip design and performance estimation of the LFSR is the problem for specific communication system. The motivation of the work is to generate the Gold code sequence by the integration of two LFSR. The article proposes the hardware chip design and simulation of two 5-bit LFSR modules used for the gold sequence generator applicable for the communication systems. The novelty of the work is that the design is scalable and can be extended based on the requirements of the systems which is synthesized and experimentally verified on the Zynq-7000 field programmable gate array (FPGA) board. The concept of this design is programmable and can be extended to n-bit based on the applications. The work is supported, and formulated using very high speed integrated circuit hardware description language (VHDL) programming in Xilinx ISE 14.7 software.</p>

A novel approach to determining the hydrodynamic resistance of droplets in microchannels using active control and grey-box system identification

Inaccurate prediction of droplet hydrodynamic resistance has a profound impact on droplet chip performance and lengthens the iterative design process. Previous studies measuring droplet resistance use various approaches such as interface comparison to quantify flow rate, and pressure taps; all these methods are classified as passive. Although each study supports well their own findings, the wide variety of conditions such as channel geometry and use of surfactant in combination with the difficulty in quantifying the droplet resistance leads to poor consensus across the different studies. Overall guidelines would be broadly beneficial to the community, but are currently fairly crude, with a rule of thumb of 2 to 5 times resistance increase. The active droplet control platform previously developed enables a novel approach that is herein confirmed as promising. This proof-of-concept study focuses on verifying this approach that employs a system identification method to determine the hydrodynamic resistance of a channel containing a single droplet, from which the droplet resistance is retrieved. This method has the potential to be further applied to a large variety of conditions, and most importantly, to non-Newtonian fluids once key limitations are overcome to improve measurement resolution. The current results qualitatively agree with the literature and demonstrate the promising future for this novel active approach to quantifying droplet resistance.

Improving Seed-Based FPGA Packing with Indirect Connection for Realization of Neural Networks

FPGAs are gaining favor among researchers in fields including artificial intelligence and big data due to their configurability and high level of parallelism. As the packing methods indisputably affect the implementation performance of FPGA chips, packing techniques play an important role in the design automation flow of FPGAs. In this paper, we propose a quantitative rule for packing priority of neural network circuits, and optimize the traditional seed-based packing methods with special primitives. The experiment result indicates that the proposed packing method achieves an average decrease of 8.45% in critical path delay compared to the VTR8.0 on Koios deep learning benchmarks.

Refined simulation method and failure study of BGA package structure based on image drive

The packaging structure, internal defects, and external loads have a significant impact on the reliability and ultimate failure of chip performance. Therefore, establishing a refined model that considers multiple factors is of great significance for improving the reliability and optimizing design of packaging structures. For this purpose, this study firstly adopts CT scanning technology to reconstruct the ball grid array (BGA) package structure in three dimensions, optimize the finite element meshing, and analyze the drop behavior by using the finite element method based on nonlinear damage instantiation. In addition, to further investigate the effect of fine defects on the failure of the package structure, a simulation of the damage evolution behavior of a real defective solder ball structure under impact loading is implemented with the help of submodeling techniques. The research results provide a technical reference for the reliability analysis and multi-occasion structure design of aerospace BGA package structures.

Evaluation of XGEN Multi Sepsis Flow Chip Molecular Assay for Early Diagnosis of Bloodstream Infection.

Among healthcare-associated infections that can affect a critically ill patient, bloodstream infections are one of the most frequent causes of mortality, especially in hospitalized patients. The objective of this work is to evaluate the performance of the XGEN Multi Sepsis Flow Chip for the rapid diagnosis of bloodstream infections compared with conventional tests. In total, 101 positive blood culture samples were included, and the results obtained by the phenotypic conventional method (culture with susceptibility profile) were compared with results obtained by the XGEN Multi Sepsis Flow Chip. This molecular assay allows the simultaneous detection of the main bloodstream infection pathogens, and their most common antibiotic resistance markers in a short period of time. It was possible to observe substantial agreement between the methods for identifying the genus of pathogens. Considering species, the agreement was excellent. In relation to susceptibility, excellent agreement was noted between the detected resistance genes and susceptibility profile obtained through conventional antibiograms. The evaluated assay presented very early and satisfactory results for identification and detection of resistance genes of the main pathogens involved in bloodstream infections.

53‐2: Mini LED Emissive Display Product with Pitch 0.5mm Based on MIP Chips

In this work, we design a new type of LED chips named MIP (Micro LED in package) chips which are composed of three or more sub‐pixel LED chips. Compared with traditional Micro LED chips, MIP can achieve EL measurement and high transfer yield. The structure and optical performance of MIP chips are demonstrated in this work. Moreover, based on MIP chips, we successfully made a Mini LED emissive display product with the pitch 0.5 mm. Such MIP chips provide a new choice for Mini LED display with small pixel pitch.

An Error Vector Magnitude Performance Modeling and Analysis Methodology for 5G mm-Wave Transmitters

This letter proposes an error vector magnitude (EVM) modeling and analysis approach for a 5G mm-wave device under test IC (DUT). This model incorporates the signal characteristics (e.g., bandwidth (BW), peak-to-average-power ratio (PAPR), and power level) and the system characteristics (e.g., intermodulation distortion (IMD) and amplitude modulation (AM–AM) <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\ldots $</tex-math> </inline-formula> ). The proposed approach accurately captures the device’s performance under study (DUT) for different device settings. The model is data-aided and compared to different modeling techniques presented in the state of the art, where it proves to be accurate in predicting the performance of a 5G mm-wave system with below 0.5% EVM error and 0.7 dB error in power across BW. Since the model predicts the DUT performance, this approach can facilitate design efforts creating expectations for chip performance postfabrication.

Design and VLSI implementation of SRAM memory array using Application-specific Integrated circuits design flow

Abstract Static Random-access memory (SRAM) are useful structure blocks in operations like data storage, embedded operations, cache recollections, microprocessors. The circuits should retain larger impunity to noise voltages. So, the Stationary Noise Margin (SNM) of the circuits should be veritably high. Large SRAM arrays that are extensively used as cache memory in microprocessors and operation-specific integrated circuits can absorb a big portion of the chip area. Highly compact circuits like SRAM arrays are estimated to cover relatively 90% of the System on chip area within the coming years. To optimize the performance of similar chips, large arrays of fast SRAM help to speed up the system performance. As a result, numerous minimal-size SRAM cells are tightly packed making SRAM arrays the compact circuitry on a chip. In this work an attempt is made to design a 8 X 8 SRAM memory array along with different components like Write driver circuit, Pre-charge circuit, Row and Column Decoder. Different SRAM architectures such as 6T, 7T and 8T are designed and different parameters such as Static Noise Margin and power dissipated are measured and the best performing memory design has been selected. 8T design has been resulted with least power dissipation. Hence this cell is selected for designing the memory array. A schematic of 8 x 8 array is designed and the layout of single SRAM 8T is created and to complete the ASIC design flow, DRC is done and the pre and post simulation are compared and verified. The integrated SRAM is operated with an input voltage of 0 to 1.8V.

Noise Reduction of Atomic Force Microscopy Measurement Data for Fitting Verification of Chemical Mechanical Planarization Model

In advanced integrated circuit manufacturing processes, the quality of chemical mechanical flattening is a key factor affecting chip performance and yield. Therefore, it has become increasingly important to develop an accurate predictive model for the chip surface topography after chemical mechanical flattening. In the modeling process, the noise problem of atomic force microscopy measurement data is relatively serious. To solve this problem, the noise characteristics of atomic force microscope measurement data for chip surface topography in this field are studied and discussed in this paper. It is found that the noise present in such problems is mainly triggered by the vibration and tilt of the probe. Two types of noise, low-frequency and high-frequency, are presented in the time domain. In order to solve the noise problem in this modeling data, this paper analyzes the spectral characteristics of the measurement data using Fourier transform, and a wavelet-Fourier transform composite noise reduction process is proposed. The algorithm is applied to the noise reduction of the chip surface data of 32 nm copper interconnect process. The noise reduction results were compared with scanning electron microscope photographs to verify the effectiveness of the noise reduction.

Worst-case Power Integrity Prediction Using Convolutional Neural Network

Power integrity analysis is an essential step in power distribution network (PDN) sign-off to ensure the performance and reliability of chips. However, with the growing PDN size and increasing scenarios to be validated, it becomes very time- and resource-consuming to conduct full-stack PDN simulation to check the power integrity for different test vectors. Recently, various works have proposed machine learning–based methods for PDN power integrity prediction, many of which still suffer from large training overhead, inefficiency, or non-scalability. Thus, this article proposed an efficient and scalable framework for the worst-case power integrity prediction, which can handle general tasks including dynamic noise prediction and bump current prediction. The framework first reduces the spatial and temporal redundancy in the PDN and input current vector and then employs efficient feature extraction as well as a novel convolutional neural network architecture to predict the worst-case power integrity. Experimental results show that the proposed framework consistently outperforms the commercial tool and the state-of-the-art machine learning method with only 0.63–1.02% mean relative error and 25–69× speedup for noise prediction and 0.22–1.06% mean relative error and 24–64× speedup for bump current prediction.

Low-Cost Indirect Measurements for Power-Efficient In-Field Optimization of Configurable Analog Front-Ends with Self-X Properties: A Hardware Implementation

This paper presents a practical implementation and measurement results of power-efficient chip performance optimization, utilizing low-cost indirect measurement methods to support self-X properties (self-calibration, self-healing, self-optimization, etc.) for in-field optimization of analog front-end sensory electronics with XFAB 0.35 µm complementary metal oxide semiconductor (CMOS) technology. The reconfigurable, fully differential indirect current-feedback instrumentation amplifier (CFIA) performance is intrinsically optimized by employing a single test sinusoidal signal stimulus and measuring the total harmonic distortion (THD) at the output. To enhance the optimization process, the experience replay particle swarm optimization (ERPSO) algorithm is utilized as an artificial intelligence (AI) agent, implemented at the hardware level, to optimize the performance characteristics of the CFIA. The ERPSO algorithm extends the selection producer capabilities of the classical PSO methodology by incorporating an experience replay buffer to mitigate the likelihood of being trapped in local optima. Furthermore, the CFIA circuit has been integrated with a simple power-monitoring module to assess the power consumption of the optimization solution, to achieve a power-efficient and reliable configuration. The optimized chip performance showed an approximate 34% increase in power efficiency while achieving a targeted THD value of −72 dB, utilizing a 1 Vp-p differential input signal with a frequency of 1 MHz, and consuming approximately 53 mW of power. Preliminary tests conducted on the fabricated chip, using the default configuration pattern extrapolated from post-layout simulations, revealed an unacceptable performance behavior of the CFIA. Nevertheless, the proposed in-field optimization successfully restored the circuit’s performance, resulting in a robust design that meets the performance achieved in the design phase.

Femtosecond-precision electronic clock distribution in CMOS chips by injecting frequency comb-extracted photocurrent pulses

A clock distribution network (CDN) is a ubiquitous on-chip element that provides synchronized clock signals to all different circuit blocks in the chip. To maximize the chip performance, today’s CDN demands lower jitter, skew, and heat dissipation. Conventionally, on-chip clock signals have been distributed in the electric voltage domain, resulting in increased jitter, skew, and heat dissipation due to clock drivers. While low-jitter optical pulses have been locally injected in the chip, research on effective distribution of such high-quality clock signals has been relatively sparse. Here, we demonstrate femtosecond-precision distribution of electronic clocks using driver-less CDNs injected by photocurrent pulses extracted from an optical frequency comb source. Femtosecond-level on-chip jitter and skew can be achieved for gigahertz-rate clocking of CMOS chips by combining ultralow comb-jitter, multiple driver-less metal-meshes, and active skew control. This work shows the potential of optical frequency combs for distributing high-quality clock signals inside high-performance integrated circuits, including 3D integrated circuits.

Experimental and numerical study on the heat transfer and flow characteristics of micro-gap chip with longitudinal vortex generator array

The longitudinal vortex generators (LVGs) are introduced in the 3D stacked chip micro gaps to enhance heat transfer. Experimental and numerical tests on the performance of 3D stacked chip with and without LVGs in the gap are conducted, and the flow and heat transfer performance at various mass flow rate and heating power as well as LVG spacing is investigated. The experimental and numerical results indicate that the LVGs array can effectively improve the cooling performance of the chip with micro gap. Under the experimental condition of q = 41 W/cm2 and Qv = 112 ml/min, the LVGs array can reduce the wall temperature by 14.49 °C compared with smooth channel. Reducing the spacing of the longitudinal vortex array can improve the cooling performance of the micro gap chip since the interaction between the vortexes generated by the LVGs in the pair is enhanced, which also causes the increase of pressure drop. The comprehensive heat transfer performance comparison considering the pump work consumption indicates that the LVGs enhanced chip is more applicable at higher heating power, and chips with smaller spacing are more applicable for conditions with lower flow rate of cooling water.

Noninvasive Detection of Bladder Cancer Markers Based on Gold Nanomushrooms and Sandwich Immunoassays

Bladder cancer is one of the most common malignancies in the urinary system. Cystoscopy is the traditional standard diagnostic method for bladder cancer with subsequent biopsy or surgery. However, this method is uncomfortable for most patients because it requires anesthesia and possibly causes infections. Because of the high recurrence rate of bladder cancer, a rapid, low-cost, high-sensitivity, and noninvasive sensing method is needed. This study employed gold nanomushroom (AuNM) chips for bladder cancer biomarker detection, combining the benefits of sandwich immunoassay and localized surface plasmon resonance (LSPR) sensing. With a metal nanotransfer printing technique, which is cheap and straightforward, the AuNMs were patterned on flexible polycarbonate (PC) sheets. The gold caps stood above PC stems and provided ample spatial areas for capturing the biomarkers to be sensed. Three biomarkers served as the antigens and analytes, including human complement factor H (CFH), hyaluronic acid (HA), and nuclear matrix protein 22 (NMP22). Different antibodies, against the same biomarker, were covalently conjugated to AuNMs or gold nanoparticles, respectively. When the antibody–antigen–antibody sandwich structure formed, the plasmonic coupling between the AuNM surface and the gold nanoparticles significantly enhanced LSPR signals. The LSPR red shifts correlated quantitatively with the concentrations of the biomarkers. The limits of detection were 6.5, 8.3, and 7.0 pg/mL for CFH, HA, and NMP22, respectively. The chip’s specificity was tested and confirmed, excluding the nonspecific binding and false-positive possibility. The sensing performance of this sandwich immunoassay-based AuNM chip was better than that of the commercialized enzyme-linked immunosorbent assay. It provided a rapid, label-free, and easy operating platform for diagnosing and monitoring bladder cancer.

Advanced Electronic Packaging Technology: From Hard to Soft

Packaging is a pivotal step in electronic device manufacturing, determining the translational performance of bare chips [...].

Compute in-Memory with Non-Volatile Elements for Neural Networks: A Review from a Co-Design Perspective.

Deep learning hasbecome ubiquitous, touching daily lives across the globe. Today, traditional computer architectures are stressed to their limits in efficiently executing the growing complexity of data and models. Compute-in-memory (CIM) can potentially play an important role in developing efficient hardware solutions that reduce data movement from compute-unit to memory, known as the von Neumann bottleneck. At its heart is a cross-bar architecture with nodal non-volatile-memory elements that performs an analog multiply-and-accumulate operation, enabling the matrix-vector-multiplications repeatedly used in all neural network workloads. The memory materials can significantly influence final system-level characteristics and chip performance, including speed, power, and classification accuracy. With an over-arching co-design viewpoint, this review assesses the use of cross-bar based CIM for neural networks, connecting the material properties and the associated design constraints and demands to application, architecture, and performance. Both digital and analog memory are considered, assessing the status for training and inference, and providing metrics for the collective set of properties non-volatile memory materials will need to demonstrate for a successful CIM technology.

Evaluation of the timing performance of the DIET ASIC

DIET is a 64-channel SiPM readout ASIC for TOF-PET and can measure energy and arrival time independently for each channel. With the increasing requirements for time measurement precision, the timing performance of the DIET chip has been fully evaluated in this paper. The noise sources in the time processing chain, especially in the TDC, were theoretically analysed, and a dedicated test system was built. The time jitter of the analogue front end and the TDC were measured and analysed. The test results show that the total jitters of the analogue front-end and the TDC are 24 ps and 22 ps RMS at 50 p.e. input signal, respectively. The percentages of the contribution by INL, thermal noise, and quantization noise of the TDC are 70%, 16.6%, and 13.4%, respectively. The DIET chip was also tested with SiPM and LYSO detectors. A CRT resolution of 244 ps FWHM was achieved using two single 3 × 3 × 16 mm3 crystals.