Test Chip Research Articles

Quantitative analysis of void initiation in thermo-mechanical fatigue of polycrystalline copper films

The early stages of thermo-mechanical fatigue in 20-μm-thick copper films are studied using accelerated stress tests on poly‑silicon heater test chips. During loading, the samples are heated up from a base temperature of 100 °C to a maximum temperature of 400 °C within 200 μs with a waiting time of 1 s between subsequent pulses. With applied heating rates up to 106 K/s, followed by studies of microstructural damage after cycle numbers between 0 and 1000, the formation of voids at grain boundaries and triple points is revealed. With image processing on scanning electron microscopy images of stressed samples, void formation and growth as a function of cycle number is quantified. The results from metallography are compared to 3D reconstructions obtained by FIB tomography.

Using correction parameters to improve real-time video interpolation in low-cost VLSI implementation

This paper introduces a relative-contrast-based algorithm to improve VLSI real-time video interpolation image quality. A relative-contrast-based adaptive interpolation correction factor wi is formed to correct linear interpolation algorithm. A LUT is integrated in proposed design to simplify the logarithmic process which is the key procedure in wi generation. Proposed algorithm improved the image quality and decline resource requirements compared with similar efforts. In comprehensive, the VLSI implementation performance shows predictably image quality improvements with sensible area cost. The chip test result shows interpolation function can support up to 1920x1080 at 60FPS, both scaler up and down.

Gain-Boosted Super Class AB OTAs Based on Nested Local Feedback

A new approach to design super class AB operational transconductance amplifiers (OTAs) with enhanced large-signal and small-signal performance is presented. It is based on employing two nested positive and negative feedback loops at the active load of an adaptively biased differential pair in weak inversion region. As a result, DC gain, gain-bandwidth product, settling time and noise are improved compared to conventional super class AB OTAs without extra circuit nodes or power consumption. Measurement results of a 180 nm CMOS test chip prototype show a current boosting factor higher than 5000 and a nearly ideal current efficiency. Due to the ultra-low quiescent currents and high driving capability, the circuit exhibits an excellent large-signal figure-of-merit (FOM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</sub> ) of 236 V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> . To illustrate the applicability of the proposed approach, a differential sample-and-hold (S/H) circuit was designed and fabricated on the same test chip. Measurement results of the S/H validate the advantages of the proposal.

A Charge-Domain Scalable-Weight In-Memory Computing Macro With Dual-SRAM Architecture for Precision-Scalable DNN Accelerators

This paper presents a charge-domain in-memory computing (IMC) macro for precision-scalable deep neural network accelerators. The proposed Dual-SRAM cell structure with coupling capacitors enables charge-domain multiply and accumulate (MAC) operation with variable-precision signed weights. Unlike prior charge-domain IMC macros that only support binary neural networks or digitally compute weighted sums for MAC operation with multi-bit weights, the proposed macro implements analog weighted sums for energy-efficient bit-scalable MAC operations with a novel series-coupled merging scheme. A test chip with a 16-kb SRAM macro is fabricated in 28-nm FDSOI process, and the measured macro throughput is 125.2-876.5 GOPS for weight bit-precision varying from 2 to 8. The macro also achieves energy efficiency ranging from 18.4 TOPS/W for 8-b weight to 119.2 TOPS/W for 2-b weight.

Demonstration of a 52-GHz Bit-Parallel Multiplier Using Low-Voltage Rapid Single-Flux-Quantum Logic

A high-throughput 4 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\boldsymbol{\times }$</tex-math></inline-formula> 4-bit multiplier was demonstrated using an extremely careful timing design for low-voltage rapid single-flux-quantum (LV-RSFQ) logic. The design considers the lengths of all wires, bias dependency of the delays, and load dependency of the signal splitters. The key is to intentionally use both Josephson transmission lines and passive transmission lines for gate-to-gate wiring, even over short distances, to form the same structure wiring as the clock lines. The structure of the multiplier is based on a bit-parallel, gate-level pipeline to exploit throughput. The test chip was fabricated using the AIST 10-kA/cm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\boldsymbol{^2}$</tex-math></inline-formula> , Nb/AlOx/Nb, 9-Nb-layer Advanced Process 2. The measured maximum operating frequency, throughput, and power consumption without cooling cost in the high-speed on-chip test were 52 GHz, 52 G-operations per second (GOPS), and 134 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\boldsymbol{\mu }$</tex-math></inline-formula> W, respectively. Although the switching speed of the Josephson junctions was reduced by 40 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\boldsymbol{\%}$</tex-math></inline-formula> owing to the low-voltage operation, the obtained clock frequency was as high as that demonstrated with the standard bias voltage. The energy efficiency was 381 tera-operations per second per watt (TOPS/W) at 4.2 K. Further improvement in energy efficiency is expected by using low-voltage half-flux-quantum (LV-HFQ) circuits and shrinking the size of Josephson junctions.

TD-SRAM: Time-Domain-Based In-Memory Computing Macro for Binary Neural Networks

In-Memory Computing (IMC), which takes advantage of analog multiplication-accumulation (MAC) insides memory, is promising to alleviate the Von-Neumann bottleneck and improve the energy efficiency of deep neural networks (DNNs). Since the time-domain (TD) computing is also an energy-efficient analog computing paradigm, we present an 8kb mixed-signal IMC macro, TD-SRAM, by combining IMC with TD computing. A dual-edge single input (DESI) TD computing topology is proposed, which can significantly improve the area and power efficiencies of TD cell. The TD-SRAM bitcell consisting of a 6T DESI based TD cell and a 6T-SRAM cell supports binary DNNs. In the IMC mode, 60 columns work in parallel and 96-input binary-MAC operations are processed in each column. Implemented in a standard 40-nm CMOS process, the TD-SRAM achieves the high energy efficiency of 537 TOPS/W at 0.9-V supply. With different DNN topologies, the test chips achieve the accuracy of 95.90%-98.00% with a dual 2-bit time-to-digital converter (TDC) in the MNIST dataset.

Effect of Aerobic Exercise Prescription Combined with Dietary Intervention on MAPK Signal Pathway in Simple Obese Children

Purpose: Observe the effect of aerobic exercise prescription combined with diet control on MAPK signaling pathways in children with simple obesity, to explore the molecular mechanisms of weight loss and health promotion in children with simple obesity. Methods: 18 male children with simple obesity were given aerobic exercise training for 4 weeks, 6 days a week, twice a day, each exercise for 2 to 2.5 hours. The dietitian formulated the corresponding diet according to the metabolic rate and weight of each subject, and strictly implemented it. And body composition, blood glucose, blood lipids, serum insulin and other indicators were test before and after the experimental. In addition, the mRNA chip was used to randomly detect the gene expression in the MAPK signaling pathway in the peripheral blood of 5 subjects before and after the experiment. Results: (1) after 4 weeks, the body shape indicators decreased significantly (p&lt;0.05); the blood glucose and lipid metabolism indicators decreased significantly (p&lt;0.05) (2) The gene chip test results found that before and after the experiment, a total of 27 genes in the MAPK signaling pathway were changed. These 27 genes were involved in the four pathways of ERK1/2, ERK5, p38 MAPK, and JNK. Conclusion: (1) 4 weeks of aerobic exercise prescription combined with diet control could significantly reduce the body fat rate of simple obese children, and could significantly improve their glucose and lipid metabolism disorder. (2) 4 weeks of aerobic exercise prescription combined with diet control could play a significant role in MAPK signaling pathway of simple obese children.

Cost-Effective Test Screening Method on 40-nm Embedded SRAMs for Low-Power MCUs

Embedded static random access memories (SRAMs) with cost-effective test screening circuitry are demonstrated for low-power microcontroller units (MCUs). The probing test step at the low temperature (LT) of -40 °C is obviated by imitating pseudo-LT (PLT) conditions in the package test, where a sample is measured at room temperature (RT). Monte Carlo simulation is carried out considering local V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> variations as well as contact soft open failure (high resistance), confirming good minimum operating voltage ( V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</sub> ) correlation between LT and PLT conditions. Test chips with two types of 4-Mbit single-port SRAM macros and 1-Mbit dual-port SRAM macro are designed and fabricated using low-power 40-nm CMOS technology. Measurement results demonstrate that the proposed test method reproduces LT conditions and screens out LT failures with less overscreening. The proposed test method eliminates 1/3 or more of the test costs.

A High-Speed and Energy-Efficient Multi-Bit Cyclic ADC Using Single-Slope Quantizer for CMOS Image Sensors

This brief proposes a high-speed and power-efficient multi-bit cyclic analog-to-digital converter (MC ADC) for CMOS image sensor applications. The proposed 13-bit MC ADC, which uses a 4-bit single-slope (SS) quantizer as a sub-ADC, resolves the sampled input voltage, followed by the cyclic SS quantization operation that repeatedly produces and quantizes the residue voltage. It operates in only seven phases to resolve 13-bit, thus achieving high conversion speed. Moreover, the 4-bit SS quantizer employs a simple and power-efficient structure that includes only the analog circuits of an operational amplifier and a comparator. A test chip with the proposed MC ADC was fabricated using a 0.18-μm standard CMOS process technology. The measurement results show that the proposed MC ADC achieves a differential nonlinearity of +0.5/-0.54 LSB and an integral nonlinearity of +1.7/-2.8 LSB. In addition, the maximum signal-to-noise-and-distortion ratio and the effective number of bits are measured to be 73.14 dB and 11.86-bit, respectively. The measured power consumption per channel is only 87 μW at a sampling frequency of 781 kHz. Moreover, the figure of merit (FoM), which includes the power consumption per channel, row line time, and ADC resolution, is only 13.6 fJ/conversion, achieving the best FoM among the compared works. Therefore, the proposed MC ADC is suitable for CMOS image sensor applications requiring high conversion speed and low power consumption, such as digital single-lens reflex cameras and ultra-high-definition television broadcast cameras.

A Total Dose Irradiation Test System

In this paper, a set of generalized test system for total dose irradiation test is designed. Through the establishment of related hardware platform and related test chip according to the adaptation requirements, the device can be observed in real time under the radiation environment. The total dose test was irradiated with the 60Co source, and it worked normally when different total doses were selected. In this article, a unit library test chip based on 130nm SOI technology is selected for testing. During the test, the system works stably and functions normally.

Plesiochronous Spread Spectrum Clocking With Guaranteed QoS for In-Band Switching Noise Reduction

Spread spectrum clocking (SSC) conventionally uses frequency modulation (FM) to suppress digital switching noise in the frequency domain. While clock-FM effectively reduces spectral noise peaks, it maintains the synchronous operation per cycle with total noise unchanged. In this paper, we introduce plesiochronous design as a general applicable de-synchronization solution for the spectral switching noise optimization with guaranteed quality-of-service. By modeling on-chip aperiodic supply current as a poly-cyclostationary random process, we theoretically prove that digital plesiochronous design contributes to reducing both, total and peak switching noise, in a harmonic frequency band of interest logarithmically proportional to the number of adopted clock domains over the synchronous baseline. A complete framework is also developed to implement plesiochronous design with the optimal clock domain partitioning and FIFO-based synchronization that features a minimum depth of six by employing Johnson encoding fully compatible with mainstream design flow. Validated on a 130nm pipelined FFT test chip across 25 dies thus taking process variations into account, our plesiochronous SSC achieves on average 5.1dB total power reductions in addition to 12.8dB peak power reductions of substrate noise at the clock fundamental frequency, which match our predictions, with only marginal hardware overhead in terms of cell area and power consumption.

Enhanced operation frequencies of bipolar double-flux-quantum amplifiers fabricated using 10 kA cm−2 Nb/AlO x /Nb integration process

We have demonstrated digital-to-analog (D/A) operations using single-flux-quantum (SFQ) pulse-frequency modulation (PFM) D/A converters for future AC voltage standards. In this paper, for the improvement of SFQ-PFM D/A converters, we investigated a double-flux-quantum amplifier (DFQA) and a magnetically-coupling SFQ driver/receiver circuit (MC-SFQ-DR) fabricated using a 10 kA cm−2 Nb/AlO x /Nb integration process. The critical current density J c of 10 kA cm−2 was four times larger than that of the integration process we had used. A DFQA and an MC-SFQ-DR included unshunted Josephson junctions, and therefore, it was unclear if the high-J c process improved their performances. We measured test chips cooled in a liquid helium bath. The maximum input voltages for a +20 fold and a −20 fold DFQA were 147 and 126 μV, for which the corresponding Josephson frequencies were 70.9 and 61.1 GHz. It was confirmed that the operation frequencies of the DFQAs and MC-SFQ-DR were improved approximately two-fold.

A Duo-Binary Transceiver With Time-Based Receiver and Voltage-Mode Time-Interleaved Mixing Transmitter for DRAM Interface

A duo-binary signaling has been applied to both transmitter and receiver for high-speed low-power DRAM interface. The transmitter consists of a half-rate voltage-mode time-interleaved mixing duo-binary driver and a 2-tap feed-forward equalizer. The voltage-mode driver is used in this brief, because it generates more linear output voltage than the current-mode driver for the duo-binary signaling at low supply voltage. A time-based receiver is used for high-speed operation at low supply voltage. A 1-tap look-ahead decision-feedback equalizer scheme was applied to the time-based receiver for the duo-binary decoding operation. The test chip fabricated in a 28 nm low-power CMOS process gives the energy efficiency of 0.41 pJ/b at 12 Gb/s with a 25 cm-long FR-4 micro-strip line and the supply voltage of 0.75V.

Test Scheduling and Test Time Reduction for SoC by Using Enhanced Firefly Algorithm

System-on-Chip (SoC) is an integration of electronic components and billions of transistors. Defects due to the base material is caused during the manufacturing of components. To overcome these issues testing of chips is necessary but total cost increases because of increasing test time. The main issues to be considered during testing of SoC are the time taken for testing and accessibility of core. Effective test scheduling should be done to minimize testing time. In this paper, an effective test scheduling mechanism to minimize testing time is proposed. The test time reduction causes test cost reduction. The Enhanced Firefly algorithm is used in this paper to minimize test time. Enhanced Firefly algorithm gives a better result than Ant colony and Firefly algorithms in terms of test time reduction thereby reduction test cost takes place.

Wide Spectrum Analysis of Human Papillomavirus Genotypes in External Anogenital Warts

External anogenital warts (EGW) are primarily associated with the low-risk human papillomavirus (HPV) genotypes 6 and 11, though coinfection with other low-risk and oncogenic high-risk HPV genotypes also occurs. Although there have been many studies on HPV-associated disease, the prevalence of HPV genotypes associated with EGW is not well characterized. The objective of our retrospective study was to determine the prevalence of HPV genotypes among patients diagnosed with EGW in the south-west of Hungary. Archived formalin-fixed paraffin-embedded tissues from 94 patients were processed in our study. HPV genotypes were determined, applying HPV Direct Flow CHIP test. The overall prevalence of HPV DNA in the EGW samples was 100%, yielding 131 infections among the 94 samples. Of these cases, 72.3% were mono while 27.6% were multi-infections. Out of the 131 infections, the cumulative prevalence of HPV 6 and 11 was 71%. A total of 98.9% of the samples were carrying at least one of these genotypes, while 19.1% of the cases occurred with at least one high-risk genotype. Data from our study could provide invaluable information concerning the prevalence of HPV types among patients with EGW, enabling improved assessment of the actual and future efficacy of vaccination programs, vaccine development, and forecast changes in infection patterns.

Converter-Free Power Delivery Using Voltage Stacking for Near/Subthreshold Operation

Integrated circuits operating in the near/subthreshold region offer low energy consumption. However, due to the constrained voltage scalability of SRAMs, efficient power delivery is difficult to achieve. A traditional implementation would require at least two distinct voltage supplies generated by possibly two power converters. In this article, a new implementation for near/subthreshold operation is presented. The proposed implementation consists of a new “converter-free” design based on a three-level voltage stack operating at 1.8 V ± 5%. Here, the leakage current from the SRAMs in the top stack is recycled to sustain the near/subthreshold operation of the logic circuits in the two lower stacks. A test chip with the proposed voltage-stacking technique was implemented in a 28-nm low- Vth (LVT) fully depleted silicon on insulator (FDSOI) technology. The test chip is an ultralow-power advanced system-on-chip (SoC) consisting of an RISC-V core, a coarse-grained reconfigurable accelerator, and peripherals. The SoC uses a current sink and an adaptive body-bias controller for voltage regulation of the intermediate voltage rails between the stacks. The proposed system achieves up to 95% power delivery efficiency with negligible area overhead (~ 1%). The silicon measurement shows that the system energy efficiency is improved by 1.6× on average, and the energy consumption is reduced by 37% on average compared to the flat implementation.

Characterization and QC practice of 16-channel ADC ASIC at cryogenic temperature for Liquid Argon TPC front-end readout electronics system in DUNE experiment

ColdADC is a low-noise 16-channel analog-to-digital converter ASIC designed for cold readout electronics of Liquid Argon Time Projection Chambers (LArTPCs) in the Deep Underground Neutrino Experiment (DUNE). ColdADC was specifically designed for operation at cryogenic temperatures (77 K–89 K). Cold electronics is considered to be an enabling technology for liquid argon detectors in neutrino experiments. The main function of the chip is to digitize signals from the 16-channel charge-sensitive amplifier designed at BNL (LArASIC) and send digitized signals to the data aggregator and serializer chip (COLDATA). ColdADC operates with a resolution of 12 bits and a sampling rate of 2 MS/s per channel. A complete characterization of prototype chips was conducted at cryogenic temperature, involving power consumption, noise and linearity performance. In the first DUNE Far-Detector module, 384000 data channels will be read out, corresponding to 24000 ColdADC chips. Therefore, systematic testing of ColdADC chips at cryogenic temperature is vital for the quality and reliability of DUNE Single-Phase modules. We have developed a Quality Control (QC) test stand that includes ColdADC evaluation and characterization at cryogenic temperature. The QC procedure was applied to a first batch of 33 chips, corresponding to 528 data channels. The obtained results meet all the required DUNE specifications for ColdADC. Moreover, the testing outcome allowed us to identify possibilities of performance optimization that are currently being addressed in the design of the next version of the chip. The Quality Control procedure is proved to be successful and will be a reference design for future large-batch production testing of final ColdADC ASICs.

A 4GS/s 8‐bit time‐interleaved SAR ADC with an energy‐efficient architecture in 130 nm CMOS

AbstractThis paper presents the design, implementation, and measurements of a 4 GS/s, 8‐bit resolution, time‐interleaved (TI) analog‐to‐digital converter (ADC) comprised of 32 asynchronous successive approximation register (SAR) ADCs. The chip is fabricated in a 130 nm CMOS process. This prototype achieves the highest sampling rate and the best efficiency for a SAR TI‐ADC in the process used. An energy‐efficient hierarchical T&amp;H architecture, ranked in a 4 × 8 structure, has been used to interleave the aforementioned high number of SAR ADCs avoiding the power hungry buffers typically used in the input signal path and/or T&amp;H outputs. The sampling architecture includes programmable delay cells with up to 104 fs resolution to calibrate sampling time errors. Additionally, the input matching network uses an on‐chip inductance to mitigate the impact of the packaging on the analog bandwidth. An efficient SAR ADC implementation is achieved by an optimized comparator design, which allows for both, noise and asynchronous clock control, and includes background DC offset calibration. The test chip is the core of a measurement platform dedicated to the evaluation of mismatch calibration techniques for ADCs used in high speed digital communication systems. To enable this application, a 32Gb/s low‐voltage differential signaling interface is included to transmit the samples off‐chip without any decimation. The TI‐ADC achieves a peak 7.09 effective number of bits (ENOB) (5.47ENOB at Nyquist) and 1.3 GHz input bandwidth with a power consumption of 93 mW at 1.2 V. Each SAR ADC channel achieves a Walden figure of merit (FOM) of 123fJ/conv‐step and owing to the efficient interleaved architecture the full TI‐ADC achieves a peak FOM of 171fJ/conv‐step (526fJ/conv‐step at Nyquist).

Fast and efficient FPGA implementation of Polar Codes and SoC test bench

In this paper we describe a novel and efficient System on Chip Field Programmable Gate Array (SoC FPGA) implementation and test bench for short Polar Codes on an Intel DE10-Standard Development Kit. Encoder and decoder are synthesized on the FPGA fabric and the whole functionality of a complete test bench is developed with an embedded ARM-based hard processor system. A Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) parametric design allows synthesis for different code lengths and is suitable for rate-adaptive decoding schemes. We implement fully-unrolled encoder and decoder architectures to achieve high troughputs and lower energy requirements, and achieve an 11% higher throughput than a reference implementation, for short Polar Codes. A novel Merged Processing Element (MPE) is optimized to be used with Sign–Magnitude LLR (SM LLR) discrete representations and pre-computing results in the decoder to reduce latency and resource consumption in comparison to reference designs. A simplified version of this MPE is also implemented, trading higher latencies for lower resource requirements. The SoC test bench design allows single-board automated testing and is also suitable for other error-correcting schemes. Error-correcting performance is evaluated for different combinations of integer and decimal part bits in LLR quantified representations. Also a new simplified non-statistical LLR metric was tested with promising results.

A 25 Gbps inductorless optical receiver analog front-end based the modified Cherry-Hooper amplifier for optical interconnect

In this paper, a 25 Gbps inductorless optical receiver analog front-end is presented. The inverter-based modified Cherry-Hooper amplifier is proposed and adopted as main stage of the optical receiver to extend the bandwidth by alleviating Miller capacitance. The optimization of shunt-feedback transimpedance amplifier is implemented by improving the gain bandwidth product of main amplifier. In multi-stage limiting amplifier, the staggered active feedback technique is used to boost the deteriorated bandwidth. Fabricated in a 55 nm CMOS technology, the whole chip occupies an area of 770 μm × 800 μm, and core area is only 100 μm × 400 μm. The measured 3-dB bandwidth reaches 21.7 GHz, sufficient for 25-Gbps operation. For an input voltage of 3 mVp-p, the chip achieves a BER = 10−12 at 25-Gbps PRBS7, and 320 mV differential output voltage is delivered. From the supply voltage of 1.2 V, the test chip consumes the power of 56 mW and exhibits the power efficiency of 2.3 pJ/s.