Test Chip Research Articles

An Efficient Inductive Rectifier Based Piezo-Energy Harvesting Using Recursive Pre-Charge and Accumulation Operation

Inductor-based rectifiers have been developed to overcome the limitations of the traditional diode-based rectifiers for piezo-energy harvesting (PEH). This article proposes a new efficient method for extracting power from the piezoelectric transducer using the inductive rectifier. In the proposed method, the internal capacitance of the transducer is initially pre-charged, and the generated charges in response to the mechanical vibration are accumulated on the capacitor. When the accumulated voltage reaches a maximum allowed value ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {MAX}}$ </tex-math></inline-formula> ), the total energy stored in the capacitor is transferred to the output, and the process is repeated. The proposed method ensures that the voltage swing across the transducer is always maximum for extracting the highest possible output power for given CMOS technology. The operational steps are self-timed, and the negative voltage swing across the transducer is avoided. The proposed inductive rectifier is realized using the buck–boost power stage of the DC energy-harvesting system for enabling efficient multi-source harvesting. Test chip is fabricated in the 180-nm CMOS technology, having a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {MAX}}$ </tex-math></inline-formula> of 3.3 V. The proposed rectifier extracts power in a single stage, even at a lower rectified output voltage <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\le $ </tex-math></inline-formula> 1 V. For a piezo open-circuit voltage of 1 V, the proposed rectifier extracts 3.68 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> more power than the maximum output power of a full-bridge rectifier with ideal diodes. This is despite the voltage loss occurring during accumulation in the power stage implementation.

A 13 Gbps 1:16 deserializer ASIC for NICA multi purpose detector project

This paper presents the design and test results of a 13 Gbps 1:16 deserializer ASIC fabricated in a 55 nm CMOS technology for Nuclotron-based Ion Collider fAcility (NICA) Multi Purpose Detector (MPD) project. The deserializer would be used in the downlink data transmission of MPD readout system to recover the serial data from the back-end to the parallel data for the front-end. The ASIC adopts a tree-type structure, consisting of a high-speed data receiver (RXDATA), a high-speed clock receiver (RXCLK), four levels of demultiplexer (DEMUX) modules, clock dividers and 16 Low-Voltage Differential Signaling (LVDS) drivers. The demultiplexer modules are composed of different numbers of high-speed DEMUX unit and low-speed DEMUX unit. The high-speed DEMUX unit and the high-frequency clock divider adopt an optimized compressed current mode logic (CML) differential structure to ensure the bandwidth with limited voltage headroom. The low-speed DEMUX unit and the low-frequency clock divider use CMOS latch to save power consumption. The duty cycle correction (DCC) circuit and the clock aligner are employed in the clock paths to ensure the correct duty cycle and aligned clock edges. In the chip test, the ASIC receives 13 Gbps serial data and outputs 16 channels of 812.5 Mbps data correctly with wide-open eye diagram. The tested power consumption is 203 mA with 1.2 V power supply including the RXDATA, the RXCLK and the 16 channels of LVDS drivers, and the core power consumption is 122.7 mA.

An Enhanced Sensitivity Operation Mode for Floating Gate Dosimeters

A new method for enhancing the sensitivity of the Floating Gate DOSimeter (FGDOS) has been investigated. By increasing the electric field in the silicon dioxide, it is possible to improve the fractional yield of collection of the electron–hole pairs, thus to increase the device’s sensitivity. In particular, a sensitivity enhancement implies a proportional improvement of the sensor’s dose resolution. Such an amelioration would dramatically improve the dosimeter’s performance in low dose rate environments, especially when only short time windows are available for measurements. Moreover, a higher electric field in the floating gate oxide makes for an improved sensitivity degradation rate throughout the device’s radiation lifetime. Results, both from analog and digital test chips, are presented, proving the effectiveness of the enhancement and its effect on the FGDOS’ sensitivity degradation rate. Finally, both aspects are discussed and explained from a theoretical point of view.

Static CMOS Physically Unclonable Function Based on 4T Voltage Divider With 0.6%–1.5% Bit Instability at 0.4–1.8 V Operation in 180 nm

This article introduces a novel class of static and monostable CMOS physically unclonable functions (PUFs) for hardware security applications. The PUF bitcell is based on a sub-threshold four-transistor (4T) voltage divider as the core block, along with an inverter as the output stage. The 4T voltage divider consists of two series-connected and nominally identical PMOS-only two-transistor (2T) circuits. This allows inherently random bit generation assisted by mismatch while also ensuring inherent robustness against environmental variations. A 180-nm test chip was characterized to validate our solution. Measurements of the 4T bitcell core prove its capability to generate random voltages with high dispersion (i.e., close to either ground or supply voltage levels) and high stability across a wide range of environmental conditions. The statistical PUF performance was evaluated on an <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$8\times32$ </tex-math></inline-formula> bitcell array without applying any post-silicon stability-enhancement technique. Raw measurements reveal a bit instability of only ~0.6% at golden key (GK) conditions (1.8 V and 25 °C), which increases up to 1.5% at 0.4 V and room temperature. When compared to prior art, our solution shows competitive performance in terms of stability, uniqueness (mean normalized inter-PUF Hamming distance (HD) of 0.493), and reproducibility (mean normalized intra-PUF HD of 0.0016), at the cost of more area-hungry design (~7200-F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> bitcell area).

A measurement structure for in-situ electrical monitoring of cyclic delamination

Cyclic delamination is the root cause for many different failure modes in semiconductor devices that are related to a loss of mechanical, electrical, or thermal contact. Some of them, such as failure due to local melting, can be considered as catastrophic. An accurate root cause analysis or precise localization of the failure is very challenging or even not possible at all. For this reason, the development of experimental methods capable of assessing early-stage delamination is desired. This work introduces a novel delamination-sensing structure integrated onto an actively heated microelectronic test chip. Actuation of the chip causes thermo-mechanical stress that initiates and drives cyclic delamination of a metallization from a functional base layer. The delamination-sensing structure allows continuous monitoring of the delamination progress by in-situ electrical resistance measurements. Its distinct geometric layout features have the effect that, when passed by a gradually advancing delamination crack front, result in characteristic responses in the monitored signal. This allows a straightforward interpretation of the measurement data without having to rely on modeling or separate calibration. The proper function of the delamination sensor is validated by a comparison of independently determined delamination distances from electrical measurements and cross-sectional inspections, respectively. Its distinguishing property of allowing a simple and time-efficient quantification of delamination is demonstrated by a study comprising 80 delamination experiments. This study investigates the effect of different heating amplitudes ΔT on the delamination rate.

Cardiac Troponin Biosensor Designs: Current Developments and Remaining Challenges.

Acute myocardial infarction (AMI) is considered as one of the main causes of death, threating human lives for decades. Currently, its diagnosis relies on electrocardiography (ECG), which has been proven to be insufficient. In this context, the efficient detection of cardiac biomarkers was proposed to overcome the limitations of ECG. In particular, the measurement of troponins, specifically cardiac troponin I (cTnI) and cardiac troponin T (cTnT), has proven to be superior in terms of sensitivity and specificity in the diagnosis of myocardial damage. As one of the most life-threatening conditions, specific and sensitive investigation methods that are fast, universally available, and cost-efficient to allow for early initiation of evidence-based, living-saving treatment are desired. In this review, we aim to present and discuss the major breakthroughs made in the development of cTnI and cTnT specific biosensor designs and analytical tools, highlighting the achieved progress as well as the remaining challenges to reach the technological goal of simple, specific, cheap, and portable testing chips for the rapid and efficient on-site detection of cardiac cTnI/cTnT biomarkers in order to diagnose and treat cardiovascular diseases at an incipient stage.

Characterization of the Total Charge and Time Duration for Single-Event Transient Voltage Pulses in a 65-nm CMOS Technology

This article presents the circuits and heavy-ion irradiation test results of a single-event transient (SET) measurement chip in a 65-nm complementary metal–oxide–semiconductor (CMOS) technology. The measurements contain two parts: total SET ionization charge and SET pulse duration. Transistors with different types and dimensions were implemented as victim devices to evaluate how transistor parameters impact the SET effects. Additionally, SET variation from different supply voltages was also investigated. The test chip has been tested under a heavy-ion beam with an effective linear energy transfer (LET) from 20.4 to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$88.35~\text {MeV}\cdot \text {cm}^{2}$ </tex-math></inline-formula> /mg using a 0°–45° incidence angle.

Long-term cultured microvascular networks on chip for tumor vascularization research and drug testing.

The vascular structure of the tumor microenvironment (TME) plays an essential role in the process of metastasis. In vitro microvascular structures that can be maintained for a long time will greatly promote metastasis research. In this study, we constructed a mimicking breast cancer invasion model based on a microfluidic chip platform, and the maintenance time of the self-assembled microvascular networks significantly improved by culturing with fibroblasts (up to 13 days). Using this model, we quantified the invasion ability of breast cancer cells and angiogenesis sprouts caused by cancer cells, and the intravasation behavior of cancer cells was also observed in sprouts. We found that cancer cells could significantly cause angiogenesis by promoting sprouting behaviors of the self-assembled human umbilical vein endothelial cells, which, in turn, promoted the invasion behavior of cancer cells. The drug test results showed that the drug resistance of the widely used anti-cancer drugs 5-Fluorouracil (5-FU) and Doxorubicin (DOX) in the 3D model was higher than that in the 2D model. Meanwhile, we also proved that 5-FU and DOX had the effect of destroying tumor blood vessels. The anti-angiogenic drug Apatinib (VEGFR inhibitor) enhanced the drug effect of DOX on MDA-MB-231 cells, further proving the promoting effect of angiogenesis on the invasion ability of cancer cells. These results indicate that our model is of great value in reconstructing TME and drug testing in vitro.

AntiDOTE: Protecting Debug Against Outsourced Test Entities

For a variety of business and technical reasons, semiconductor companies might choose to outsource fabrication, assembly, and testing. To fulfill their obligations, external foundries and test houses need access to chip test interfaces to ensure basic functionality. These test interfaces must be protected against illegitimate accesses to prevent extraction of sensitive original equipment manufacturer (OEM) and end-user data from devices in the field as well as thwart intellectual property (IP) piracy and overproduction of integrated circuits. In this article, we present AntiDOTE, a low-cost and robust access control mechanism for test interfaces that supports outsourced fabrication, assembly, and testing with untrusted foundries and testers without compromising security. We showcase AntiDOTE on an ARM Cortex M0-based micro-controller fabricated using commercially available 55nm technology.

A comprehensive framework for cell-aware diagnosis of customer returns

The first step when a customer return occurs in industry is to reproduce the failure mechanism with any original test and test conditions (voltage, temperature, etc.) used during initial post-fabrication test. Depending on the test scenario (test sequence, test scheme, test conditions), different types of defects and failure mechanisms are targeted, thus leading to different diagnosis outcomes. Based on our previous work, this paper presents a comprehensible framework for cell-aware diagnosis of customer returns. The first part of the paper summarizes our previous work in which a generic cell-aware diagnosis flow using a Bayesian classification method was proposed to precisely identify defect candidates in combinational cells of a defective circuit according to a given test scenario. The second part of the paper extends the previous work by dealing with defects in sequential cells of defective circuits. New experiments done on a silicon test chip and a customer return with a given test scenario have proven the efficacy of our flow in terms of diagnosis accuracy and resolution.

The Tangerine project: Development of high-resolution 65 nm silicon MAPS

The Tangerine project aims to develop new state-of-the-art high-precision silicon detectors. Part of the project has the goal of developing a monolithic active pixel sensor using a novel 65 nm CMOS imaging process, with a small collection electrode. This is the first application of this process in particle physics, and it is of great interest as it allows for an increased logic density and reduced power consumption and material budget compared to other processes. The process is envisioned to be used in for example the next ALICE inner tracker upgrade, and in experiments at the electron-ion collider.The initial goal of the three-year Tangerine project is to develop and test a sensor in a 65 nm CMOS imaging process that can be used in test beam telescopes at DESY, providing excellent spatial resolution and high time resolution, and thus demonstrating the capabilities of the process. The project covers all aspects of sensor R&D, from electronics and sensor design using simulations, to prototype test chip characterisation in labs and at test beams. The sensor design simulations are performed by using a powerful combination of detailed electric field simulations using technology computer-aided design and high-statistics Monte Carlo simulations using the Allpix2 framework. A first prototype test chip in the process has been designed and produced, and successfully operated and tested both in labs and at test beams.

A 0.6V–1.8V Compact Temperature Sensor With 0.24 °C Resolution, ±1.4 °C Inaccuracy and 1.06nJ per Conversion

This paper presents a fully-integrated CMOS temperature sensor for densely-distributed thermal monitoring in systems on chip supporting dynamic voltage and frequency scaling. The sensor front-end exploits a sub-threshold PMOS-based circuit to convert the local temperature into two biasing currents. These are then used to define two oscillation frequencies, whose ratio is proportional to absolute-temperature. Finally, the sensor back-end translates such frequency ratio into the digital temperature code. Thanks to its low-complexity architecture, the proposed design achieves a very compact footprint along with low-power consumption and high accuracy in a wide temperature range. Moreover, thanks to a simple embedded line regulation mechanism, our sensor supports voltage-scalability. The design was prototyped in a 180nm CMOS technology with a 0{\deg}C $-$ 100{\deg}C temperature detection range, a very wide supply voltage operating range from 0.6V up to 1.8V and very small silicon area occupation of just 0.021$mm^2$. Experimental measurements performed on 20 test chips have shown very competitive figures of merit, including a resolution of 0.24{\deg}C, an inaccuracy of $\pm$1.4{\deg}C, a sampling rate of about 1.5kHz and an energy per conversion of 1.06nJ at 30{\deg}C.

BitBlade: Energy-Efficient Variable Bit-Precision Hardware Accelerator for Quantized Neural Networks

We introduce an area/energy-efficient precision-scalable neural network accelerator architecture. Previous precision-scalable hardware accelerators have limitations such as the under-utilization of multipliers for low bit-width operations and the large area overhead to support various bit precisions. To mitigate the problems, we first propose a bitwise summation, which reduces the area overhead for the bit-width scaling. In addition, we present a channel-wise aligning scheme (CAS) to efficiently fetch inputs and weights from on-chip SRAM buffers and a channel-first and pixel-last tiling (CFPL) scheme to maximize the utilization of multipliers on various kernel sizes. A test chip was implemented in 28-nm CMOS technology, and the experimental results show that the throughput and energy efficiency of our chip are up to 7.7 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> and 1.64 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> higher than those of the state-of-the-art designs, respectively. Moreover, additional 1.5–3.4 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> throughput gains can be achieved using the CFPL method compared to the CAS.

A 65 nm 73 kb SRAM-Based Computing-In-Memory Macro With Dynamic-Sparsity Controlling

For neural network (NN) applications at the edge of AI, computing-in-memory (CIM) demonstrates promising energy efficiency. However, when the network size grows while fulfilling the accuracy requirements of increasingly complicated application scenarios, significant memory consumption becomes an issue. Model pruning is a typical compression approach for solving this problem, but it does not fully exploit the energy efficiency advantage of conventional CIMs, because of the dynamic distribution of sparse weights and the increased data movement energy consumption of reading sparsity indexes from outside the chip. Therefore, we propose a vector-wise dynamic-sparsity controlling and computing in-memory structure (DS-CIM) that accomplishes both sparsity control and computation of weights in SRAM, to improve the energy efficiency of the vector-wise sparse pruning model. Implemented in a 65 nm CMOS process, the measurement results show that the proposed DS-CIM macro can save up to 50.4% of computational energy consumption, while ensuring the accuracy of vector-wise pruning models. The test chip can also achieve 87.88% accuracy on the CIFAR-10 dataset at 4-bit precision in inputs and weights, and it achieves 530.2TOPS/W (normalized to 1 bit) energy efficiency.

A 6T SRAM Based Two-Dimensional Configurable Challenge-Response PUF for Portable Devices

This work proposes a 2-dimensional programable SRAM-based PUF. The selection of challenge groups, orders, and sequence lengths dominates the responses with challenge-response pairs (CRPs) by order of rows<inline-formula> <tex-math notation="LaTeX">$^{\mathrm {(sequence~\textrm {}length- 1)}} \times $ </tex-math></inline-formula> columns<inline-formula> <tex-math notation="LaTeX">$^{\mathrm {(sequence~\textrm {}length - 1)}}$ </tex-math></inline-formula>. The PUF bit cell has split word-lines with vertical and horizontal connections, the bit-lines are placed orthogonally to generate one-bit data with four cells, the entropy source is enriched to 24 transistors. The proposed PUF supports multiple data maps from a single chip. A test chip was fabricated in 65 nm CMOS technology. Under 0.8V and 20 &#x00B0;C (nominal point), the bit error rate reaches 3&#x0025;. In a single chip, the hamming distance achieves 42.49&#x0025; within the same group and different orders of challenges, and 47.32&#x0025; within the different groups of challenges (when the sequence length is 5). The measured inter-hamming distance between chips is improved to 49.47&#x0025;.

SRAM-Based In-Memory Computing Macro Featuring Voltage-Mode Accumulator and Row-by-Row ADC for Processing Neural Networks

This paper presents a mixed-signal SRAM-based in-memory computing (IMC) macro for processing binarized neural networks. The IMC macro consists of <inline-formula> <tex-math notation="LaTeX">$128\times 128$ </tex-math></inline-formula> (16K) SRAM-based bitcells. Each bitcell consists of a standard 6T SRAM bitcell, an XNOR-based binary multiplier, and a pseudo-differential voltage-mode driver (i.e., an accumulator unit). Multiply-and-accumulate (MAC) operations between 64 pairs of inputs and weights (stored in the first 64 SRAM bitcells) are performed in 128 rows of the macro, all in parallel. A weight-stationary architecture, which minimizes off-chip memory accesses, effectively reduces energy-hungry data communications. A row-by-row analog-to-digital converter (ADC) based on 32 replica bitcells and a sense amplifier reduces the ADC area overhead and compensates for nonlinearity and variation. The ADC converts the MAC result from each row to an N-bit digital output taking 2^N-1 cycles per conversion by sweeping the reference level of 32 replica bitcells. The remaining 32 replica bitcells in the row are utilized for offset calibration. In addition, this paper presents a pseudo-differential voltage-mode accumulator to address issues in the current-mode or single-ended voltage-mode accumulator. A test chip including a 16Kbit SRAM IMC bitcell array is fabricated using a 65nm CMOS technology. The measured energy- and area-efficiency is 741-87TOPS/W with 1-5bit ADC at 0.5V supply and 3.97TOPS/mm², respectively.

Hardware Performance Monitoring Methodology at Near-Threshold Computing and Advanced Technology Nodes: From Design to Postsilicon

Near-threshold computing is essential for energy-efficient operation of VLSI systems, but wide performance variation and nonlinearity to process variations block the proliferation. To cope with this, in this article, we propose a holistic hardware performance monitoring methodology for accurate timing prediction in a near-threshold voltage regime. Precisely, 1) we formulate the problem of finding an efficient configuration of monitoring circuits into an instance of optimal experiment design problem and 2) propose a new timing prediction flow, consisting of statistical estimation of FEOL and BEOL process variations and a neural network-based timing inference model. For accurate control of timing margin and overcoming simulation-silicon discrepancies, 3) we introduce uncertainty learning in the prediction model construction and calibrate it through transfer learning. Furthermore, 4) we avoid time-consuming SPICE simulations in our methodology by employing efficient but accurate surrogate models. Through simulations using a 28-nm industry PDK and DK characterized at 0.6-V operation, it is shown that our methodology is highly effective, reducing the average prediction pessimism of maximum delay by 77.9% over conventional signoff results while respecting target prediction yield. Besides, for test chips fabricated using a 10-nm process, we demonstrated that our holistic approach from design to postsilicon phase in conjunction with adaptive voltage scaling reduces dynamic power consumption by 28.2%–28.8% on average, in comparison with typical supply voltage operation.

Application of Three-Repetition Tests Scheme to Improve Integrated Circuits Test Quality to Near-Zero Defect.

In this research, the normal distribution is assumed to be the product characteristic, and the DITM (Digital Integrated Circuit Test Model) model is used to evaluate the integrated circuits (IC) test yield and test quality. Testing technology lags far behind manufacturing technology due to the different rates of development of the two technologies. As a result, quality control will pose significant challenges in pursuing high-quality near-zero defect products (automotive and biomedical electronics and avionics, etc.). In order to ensure product quality, we propose an effective repeated testing method (three-repetition tests scheme, TRTS), which utilizes the move test guardband (TGB) to improve the test yield and test quality. Based on the data in the International Roadmap for Devices and Systems table in 2021, the DITM model is used to estimate the future trend of semiconductor chip test yield, and the retest method (TRTS) is applied improve the test results. The method of repeated testing can increase the test yield and increase the shipment of semiconductor products. By estimating the test cost and profit, the method of repeated testing can obtain chips with near-zero defects with more corporate profits through increased product shipments.

Time-Varying Pseudorandom Disturbed Pattern Generation Algorithm for Track Circuit Equipment Testing.

To improve the test accuracy and fault coverage of high-speed railway-related equipment boards, a time-varying pseudorandom disturbance algorithm based on the automatic test pattern generation technology in chip testing is proposed. The algorithm combines the pseudorandom pattern generation algorithm with the deterministic pattern generation D algorithm. The existing pseudorandom number generation method usually requires random seeds to generate a series of pseudorandom numbers. In this algorithm, the system timer is used as the random seed to design a pseudorandom pattern generation method of time-varying seed to improve the randomness of pseudorandom pattern generation. In addition, in combination with the D algorithm, this work proposes a new switching logic between two algorithms by counting invalid pattern proportions. When the algorithm is applied to track a circuit netlist, the fault coverage can reach near 100%. However, the large-scale circuit fault coverage cannot easily reach 100%. The test results for the standard circuits of different sizes show that at the same time, compared with the independent pattern generation methods, the proposed algorithm can improve fault coverage by more than 50% and 30% and significantly improve the pattern generation efficiency. Therefore, it can be used perfectly in the subsequent construction of high-speed railway equipment test platforms.

High Prevalence of Non-Vaccinated Oncogenic Human Papillomavirus Genotypes in High-Grade Squamous Intraepithelial Lesions of the Cervix: Thought-Provoking Results of a Detailed HPV Genotype Analysis.

Identification of HPV infection is usually performed on cytological specimens, despite the often transient virus types. HPV profile analysis of pathologically confirmed lesions can also be performed on formalin-fixed paraffin-embedded (FFPE) cone samples and should be taken as standard during follow-up. We compared HPV profiles of cytological and FFPE specimens of women diagnosed with HSIL. Archived PAP smears and FFPE cones from 49 patients were processed. For genotyping, the HPV Direct Flow CHIP test was used. All samples were positive. HPV profile agreement of the two sample types was 84.16–100%. Mono-infections occurred in 12.24% and 61.22% in PAP smears and FFPE specimens, respectively; while multi-infections were detected in 87.76% and 38.78%, respectively. The most abundant genotypes were HPVs 16, 31, and 51/33. Of all infections, 56.25% and 64.93% were caused by nonavalent vaccinated type (VT) HPVs; while 50.69% and 38.96% belonged to non-nonavalent VT HPVs, in PAP smears and FFPE specimens, respectively. Our results confirmed the importance of HPV genotyping of FFPE cone samples. We also confirmed a remarkable presence of non-vaccinated HPV types in HSIL cases indicating the importance of vaccine development.