Test Chip Research Articles

SRAM Write Assist Circuit Using Cell Supply Voltage Self-Collapse With Bitline Charge Sharing for Near-Threshold Operation

This brief presents SRAM write assist circuit using cell supply voltage self-collapse with bitline charge sharing (SC-BCS) that can lower the minimum operating voltage to the near-threshold voltage (Vth) region while consuming a minimal write energy. The proposed SC-BCS improves the write-ability by utilizing the cell supply voltage (CVDD) self-collapse and the feedback operation through the detection of write failure. Because the amount of CVDD collapse is regulated automatically depending on the write-ability of the selected cell, the write energy of the proposed SC-BCS is effectively reduced. The proposed SC-BCS can achieve a 5σ write-ability yield with a smaller delay overhead than gate-modulated self-collapse and self-collapse write assists in the near-Vth region. In addition, the proposed SC-BCS consumes the lowest write energy with minimal delay overhead or without any delay overhead compared with the strong-bias transient CVDD collapse and pulsed-pMOS transient CVDD collapse. The measurement result of the test chip fabricated using 65-nm CMOS technology indicates that the proposed SC-BCS can operate without any failure up to 0.36 V consuming write power 12.6 μW/MHz.

Yield and leakage current of organic thin-film transistor logic gates toward reliable and low-power operation of large-scale logic circuits for IoT nodes

This paper reports on a strategy for yield improvement and static leakage current reduction by a standard cell design for large-scale organic thin-film transistor (OTFT) circuits. Printable or flexible devices are suitable for IoT nodes, and digital OTFT circuits comprise the peripheral circuits of such devices. Sufficiently high yields and low static power consumptions are essential for battery operations of IoT nodes having functional digital circuits. Our design method to address the weak n-type OTFT on-current results in improved logic gate yields without any cell area increase. We improved the yield of the inverter, NAND, and NOR gates using a standard cell design, and achieved a 100% yield for the inverter and NOR gates and 88% yield for the NAND gates. Signal propagations with the rail-to-rail operation were measured on test chips. Leakage currents of 585 pA and 2.94 nA were achieved for the inverter and NOR gates, respectively.

A Referenceless Digital CDR with a Half-Rate Jitter-Tolerant FD and a Multi-Bit Decimator

A referenceless digital clock and data recovery (D-CDR) circuit using a half-rate jitter-tolerant frequency detector (FD) and a multi-bit decimator is presented. For a referenceless configuration, we introduced a half-rate jitter-tolerant digital quadricorrelator frequency detector (JT-DQFD). Additionally, we proposed a multi-bit decimator circuit that losslessly down-samples up/down data from a phase detector to reduce the recovered clock jitter. The down-sampled multi-bit phase information is processed by a digital loop filter to adjust the phase of the recovered clock. Fabricated in a 28-nm CMOS technology, the test chip achieves a power efficiency of 1.3 pJ/bit at 10 Gb/s.

The Research on the Signal Generation Method and Digital Pre-Processing Based on Time-Interleaved Digital-to-Analog Converter for Analog-to-Digital Converter Testing

In the high-resolution analog circuit, the performance of chips is an important part. The performance of the chips needs to be determined by testing. According to the test requirements, stimulus signal with better quality and performance is necessary. The main research direction is how to generate high-resolution and high-speed analog signal when there is no suitable high-resolution and high-speed digital-to-analog converter (DAC) chip available. In this paper, we take the high-resolution analog-to-digital converter (ADC) chips test as an example; this article uses high-resolution DAC chips and multiplexers to generate high-resolution high-speed signals that can be used for testing high-resolution ADC chips based on the principle of time-alternating sampling. This article explains its method, analyzes its error and proposes a digital pre-processing method to reduce the error. Finally, the actual circuit is designed, and the method is verified on the circuit. The test results prove the effectiveness of this method for generating high-resolution ADC test signals.

A High Reliable SRAM-Based PUF With Enhanced Challenge-Response Space

This brief proposes a sequence-dependent SRAM-based PUF with enhanced reliability. It expands the CPRs by order of (rows <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{(sequence\,\,length\,\,}{}^{+}{}^{\,\,}{}^{2}{}^{)}\,\, \mathbf {\mathrm {\times }}$ </tex-math></inline-formula> columns) for reliable authentication. The proposed bitcell utilizes split word-lines to control two access transistors separately. The PUF mode turns on two left word-lines and two right word-lines simultaneously, including 18 transistors for generating one-bit data. This proposed technique supports rendering multiple data maps from one chip. Besides, various temperature and voltage combinations can create a reliability map for each data map. A test chip was fabricated in 40 nm CMOS technology. The measured worst bit error rate is 0.8% at the nominal point (1V, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$20 \mathbf {\mathrm {^\circ }}$ </tex-math></inline-formula> C). From a single chip, the proposed PUF achieved the hamming distances of 41.29% for one sequence with different orders and 44.93% for other sequences, respectively. The measured inter-chip hamming distance is 49.64%.

A 6-Gb/s Inductively-Powered Non-Contact Connector With Rotatable Transmission Line Coupler and Interface Bridge IC

A 6 Gb/s 9.8 pJ/b rotatable non-contact connector applicable to industrial robot arms is developed. The proposed non-contact connector enables a high-speed and highly reliable wireless data connection between three-dimensional (3-D) cameras and an edge computer in an autonomously controlled robot. A rotatable transmission line coupler (RTLC) is proposed to accommodate the rotational operation of the robot arm. Since the proposed doughnut-shaped RTLC has a constant overlapped area at any rotation angle, the RTLC has a constant coupling gain at all rotation angles. To remove inter-symbol interference (ISI) occurring at a specific rotation angle, a pulse-equalizing receiver is also developed. An interface bridge IC is proposed to transfer a wide range of interface signals from a slow-control signal such as the control area network (CAN) to a high-speed video interface signal. A signal protocol conversion technique applying on-off keying (OOK) modulation is also developed in order to transfer slow legacy interfaces used in the robot arms that include a dc component. Experiments with a test chip fabricated in a 40 nm CMOS process confirmed that bit error rate (BER) was lower than 10 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-12}$ </tex-math></inline-formula> at any rotation angle in a communication distance of 3 mm. The proposed system improves energy efficiency by a factor of 3.7, area efficiency by a factor of 1.8.

Evaluation and Optimization of a Cross-Rib Micro-Channel Heat Sink.

This article presents a novel cross-rib micro-channel (MC-CR) heat sink to make fluid self-rotate. For a thermal test chip (TTC) with 100 w/cm2, the cross-ribs micro-channel were compared with the rectangular (MC-R) and horizontal rib micro-channel (MC-HR) heat sinks. The results show that, with the cross-rib micro-channel, the junction temperature of the thermal test chip was 336.49 K, and the pressure drop was 22 kPa. Compared with the rectangular and horizontal ribs heat sink, the cross-rib micro-channel had improvements of 28.6% and 14.3% in cooling capability, but the pressure drop increased by 10.7-fold and 5.5-fold, respectively. Then, the effects of the aspect ratio (λ) of micro-channel in different flow rates were studied. It was found that the aspect ratio and cooling performance were non-linear. To reduce the pressure drop, the inclination (α) and spacing (S) of the cross-ribs were optimized. When α = 30°, S = 0.1 mm, and λ = 4, the pressure drop was reduced from 22 kPa to 4.5 kPa. In addition, the heat dissipation performance of the rectangular, staggered fin (MC-SF), staggered rib (MC-SR) and cross-rib micro-channels were analyzed in the condition of the same pressure drop, MC-CR still has superior heat dissipation performance.

A CMOS Integrator-Based Clock-Free Time-to-Digital Converter for Home-Monitoring LiDAR Sensors.

This paper presents a nine-bit integrator-based time-to-digital converter (I-TDC) realized in a 180 nm CMOS technology for the applications of indoor home-monitoring light detection and ranging (LiDAR) sensors. The proposed I-TDC exploits a clock-free configuration so as to discard clock-related dynamic power consumption and some notorious issues such as skew, glitch, and synchronization. It consists of a one-dimensional (1D) flash TDC to generate coarse-control codes and an integrator with a peak detection and hold (PDH) circuit to produce fine-control codes. A thermometer-to-binary converter is added to the 1D flash TDC, yielding four-bit coarse codes so that the measured detection range can be represented by nine-bit digital codes in total. Test chips of the proposed I-TDC demonstrate the measured results of the 53 dB dynamic range, i.e., the maximum detection range of 33.6 m and the minimum range of 7.5 cm. The chip core occupies the area of 0.14 × 1.4 mm2, with the power dissipation of 1.6 mW from a single 1.2-V supply.

A set of hysteretic nonlinear contact models for DEM: Theory, formulation, and application for lignocellulosic biomass

A monosphere discrete element method (DEM) model is introduced for elucidating the bulk mechanical behavior of granular biomass. This model considers each sphere as a representative elementary volume in bulk particles and is highly scalable in computation. To compensate for the simplification of particle shapes, we propose a set of hysteretic nonlinear contact models for approximating the bulk strain-hardening phenomena of granular biomass in handling and storage conditions. These contact models comprise of simple polynomial and/or exponential functions to allow for easy calibration. To ensure numerical stability, we have derived unconditionally stabilized viscous damping force models. The resultant DEM model is implemented in LIGGGHTS-INL and applied to simulate an axial compressibility test for milled pine chips. Results show that the DEM model can reproduce the bulk stress–strain profiles of the physical samples and that the predicted bulk compressibility and constrained modulus under repeated compression agree reasonably with the experimental data.

Experimental Characterization of Multitone EM Immunity of Integrated Oscillators Under Thermal Stress

The reliable operation of an integrated circuit can be affected by environmental changes, such as of multiple frequency electromagnetic (EM) disturbances and temperature variations. This paper compares the performance of two oscillator circuits, namely a current-starved voltage controlled oscillator and a ring oscillator integrated into a chip, in terms of their immunity to multitone direct power injection while under the influence of thermal stress. The objective is to demonstrate by the means of measurements the synergistic effect caused by multitone EM disturbances in a test chip, in contrast to the conventional single-tone EM disturbances. Moreover, the multitone immunity levels of integrated blocks with different architectures but similar functionality are analyzed at extreme temperature deviations. Bayesian networks (BN) are applied in order to visualize the probability of circuit failure due to multitone disturbances and temperature influence. Additionally, noisy-OR and improved-adaptive-recursive-noisy-OR (I-ARNOR) probabilistic models are implemented to identify the types of causal interactions (i.e. inhibition and positive causality) between multitone disturbances and to predict the probability of failure due to higher order multitone disturbances, respectively.

Active-Matrix Pixelated-LED Control System for Automotive Headlamps

This paper presents a driving circuitry system for high-resolution, pixelated-LED automotive headlamps. The system consists of an array of pixel drivers, and a row/column driver suitable for an active-matrix array configuration with the individual dimming control capabilities on each pixelated-LED. An asynchronous serial communication protocol is introduced to minimize the number of data transmission interface signals between the row/column driver and pixel drivers. The proposed pixel driver is designed to drive each pixelated-LED with constant current and pulse width modulation (PWM). It contains a memory cell for dimming data, and a sample-and-hold driver stage to minimize the static power consumption of the pixel driver. The proposed system has been fabricated by using a 0.18-μm CMOS process. The test chip includes a 2 × 16 pixel array with an embedded row/column driver. The functional operation has been verified with an 8 × 16 LED array system prototype.

A 17-mW 0.5–1.5-GHz Bandwidth TIA Based on an Inductor-Stabilized OTA With 35–42-dBm In-Band IIP3

A transimpedance amplifier (TIA) is presented for 5G and future mobile standards. The bandwidth of the TIA can be programmed from 500 MHz to 1.5 GHz. The operational transconductance amplifier (OTA) is designed combining feedforward compensation and inductive peaking, to ensure loop stability and obtain high loop gain with low-power dissipation. TSMC 28-nm HPC technology was used to implement a test chip. With a power dissipation of 17 mW, the TIA achieves an in-band IIP3 ranging from 35 to 42 dBm and output integrated noise of 300 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula> Vrms.

A 40-nm, 64-Kb, 56.67 TOPS/W Voltage-Sensing Computing-In-Memory/Digital RRAM Macro Supporting Iterative Write With Verification and Online Read-Disturb Detection

Computing-in-memory (CIM) architectures have gained importance in achieving high-throughput energy-efficient artificial intelligence (AI) systems. Resistive RAM (RRAM) is a promising candidate for CIM architectures due to a multiply-and-accumulate (MAC)-friendly structure, high bit density, compatibility with a CMOS process, and nonvolatility. Notwithstanding the advancement of RRAM technology, the reliability of an RRAM array hinders the spread of RRAM applications such that a circuit-technology joint approach is necessary to attain reliable RRAM-based CIM architectures. This article presents a 64-kb hybrid CIM/digital RRAM macro supporting: 1) active-feedback-based voltage-sensing read (RD) to enable 1–8-b programmable vector-matrix multiplication under a low-resistance ratio of the high-resistance state to the low-resistance state in an RRAM array; 2) iterative write with verification to secure a tight resistance distribution; and 3) online RD-disturb detection in the background during CIM. The test chip fabricated in a 40-nm CMOS and RRAM process achieves a peak energy efficiency of 56.67 TOPS/W while demonstrating the eight-bitline hybrid CIM/digital MAC operation with 1–8-b inputs and weights and 20-b outputs without quantization.

A Dual-Entropy-Superposed PUF With In-Cell Entropy Sign-Based Stabilization

In this paper, we present a novel physical unclonable function (PUF) based on dual entropy sources of a 2-transistor voltage reference (2T-VR) and a four-stage diode-clamped comparator. Featuring excellent stability over wide range of supply voltage and temperature, the proposed 2T-VR is constructed with one native transistor plus one PMOS transistor that are compensated to minimize its temperature coefficient. Moreover, different from most previous PUF implementations where a digital comparator with offset-cancellation is needed for digitizing the mismatched voltages/currents from the prior entropy stage, in this work, the customized diode-clamped comparator’s offset is well-exploited as an additional entropy source, which can be superposed on the above 2T-VR-based entropy to significantly elevate the whole PUF structure’s reliability. Besides, a near zero-overhead in-cell entropy sign based stabilization (ESS) scheme is proposed to further enhance the reliability by stabilizing the scenario with the dual entropy sources having opposite signs. The designed dual-entropy-superposed PUF is fabricated using a 65-nm standard CMOS process, and its excellent randomness is validated using the widely-accepted National Institute of Standards and Technology (NIST) PUB 800-22/800-90B and autocorrelation function (ACF) test tools. With the test chips repeatedly challenged at normal condition up to 4000 times, the measured native bit error rate (BER) and unstable bits are reported to be 0.16% and 1.3%, respectively. Moreover, with the operating temperature changing from −50°C to 130°C and the supply voltage changing from 0.8 V to 1.4 V, the native BER’s VT sensitivities without stabilization are measured to be 0.195%/10°C and 0.651%/0.1 V, respectively, which can be further reduced by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.5\times $ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.5\times $ </tex-math></inline-formula> with the proposed ESS scheme applied.

A Novel Multi-Scale Method for Thermo-Mechanical Simulation of Power Integrated Circuits

During development of power Integrated Circuits (IC), several iterations between the design and test/ measurement steps are performed. Computer-aided engineering significantly shortens the product development process because the numerical simulations can identify and remediate most deficiencies during the design stage. The recent IC manufacturing technologies lead to ca. <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{4}$ </tex-math></inline-formula> -order scale separation between transistor cell details and the device active area, resulting in very complex IC models. For the IC complexity to be overcome, advanced multi-scale analysis methods are required to perform accurate simulations in a decent time (order of hours). This paper proposes an advanced and enhanced multi-scale simulation method for the thermo-mechanical analysis of power ICs. The computational IC structure is automatically generated from a Cadence layout and partitioned into far-field and homogenized regions - the macro-model. Detailed localized micro-scale sub-models are assigned to limited portions of the homogenized region. The two-way simulated data transfer between the homogenized macro-model and the micro sub-models is one multi-scale approach novelty proposed in this paper. The method is validated on a real test chip structure presented in literature. The proposed multi-scale approach in conjunction with the two-way macro-micro data transfer lead to similar accuracy in the prediction of defect location, yet with significant simulation time - and computational resource reduction (CPU time and RAM usage reduced by almost 80% and 60% respectively) compared to the method used as reference.

5-nm Low-Power SRAM Featuring Dual-Rail Architecture With Voltage-Tracking Assist Circuit for 5G Mobile Application

Voltage Auto Tracking Cell Power Lowering (VACPL) write assist circuit and Voltage Auto Tracking Assist (VATA) are proposed for low-power SRAM with dual-rail architecture to mitigate the SRAM design margin issues. VACPL controls the cell voltage adaptively with respect to the dual rail offset voltage to maximize bitcell write-ability. The access disturb is recovered by lowering WL voltage level with VATA at the large dual rail offset voltage condition. A 5 nm EUV FinFET test chip demonstrates 210 mV VMIN improvement and 4.7x larger range of operating voltage with VACPL. The proposed VACPL and VATA achieves 95.2% leakage power reduction by lowering VDDC by 400 mV in 5 nm 5G mobile device.

Syn-STELLAR: An EM/Power SCA-Resilient AES-256 With Synthesis-Friendly Signature Attenuation

Mathematically secure cryptographic algorithms leak meaningful side-channel information in the form of correlated power and electromagnetic (EM) signals, leading to physical side-channel analysis (SCA) attacks. Circuit-level countermeasures against power/EM SCA include a current equalizer, IVR, non-linear LDOs, enhancing protection up to 10M traces, and current-domain signature attenuation (CDSA), and randomized NL-LDO cascaded with arithmetic countermeasures achieved protection up to >1B. This work embraces the concept of analog CDSA but makes it easily scalable over technology nodes with digital-friendly current sources, digital control loop, and digital bleed path to increase the MTD from 10M to 250M (25x improvement, using a single digital countermeasure). Ring oscillator (RO) used as the bleed path to bypass encryption-dependent leakage acts as local negative feedback (LNFB). Besides, based on RO oscillation frequency, AES node voltage can be tuned at startup, PVT, or frequency variation. Thus, RO acts as integrated LNFB and global feedback for the digital signature attenuation circuit (DSAC). Another circuit technique, namely, the time-varying transfer function (TVTF), removes the requirement of dc bias in the current-domain equalizer (best switch capacitor-based countermeasure till date) to make it digital and utilizes switch cap-based circuit for time-domain obfuscation to achieve enhanced security. This work, namely, Syn-STELLAR: SYNthesis-friendly Signature aTtenuation Embedded crypto with Low-Level metAl Routing, combines both DSAC and TVTF techniques to achieve an MTD>1.25B for both EM and power SCA, which is 25% higher than the existing state of the art. The 65-nm CMOS test chip contains unprotected and both the protected (DSAC and DSAC-TVTF) parallel AES-256 implementation. This implementation is the first synthesis-friendly countermeasure, which converges two analog-type strong protections (signature attenuation and switched cap current equalizer) in a digital-friendly solution and achieves >1.25B MTD with power and area overheads comparable to previous circuit-level countermeasures.

A High-Efficiency Segmented Reconfigurable Cyclic Shifter for 5G QC-LDPC Decoder

A reconfigurable cyclic shifter is a key element of a QC-LDPC decoder, which is crucial for 5G communication systems. If a traditional reconfigurable cyclic shifter can only shift one input of variable size at a time, a traditional QC-LDPC decoder can only decode one codeword at a time as well. Part of the circuitry of the traditional QC-LDPC decoder inevitably stays in idle during the decoding process if the length (or the lifting parameter) of a codeword is not the maximum, resulting in low hardware efficiency. A segmented reconfigurable cyclic shifter is proposed in this paper, which can be divided into multiple segments of different sizes. Each segment can perform a cyclic shift of an input of different sizes and of different shift values independently. Furthermore, a methodology is proposed to upgrade any state-of-the-art QC-LDPC decoder to a segmented QC-LDPC decoder, by using the proposed segmented shifter. The upgraded segmented QC-LDPC decoder is able to parallelly decode multiple codewords (or inputs) of different lengths at a time. A test chip of the proposed segmented QC-LDPC decoder with the proposed segmented reconfigurable cyclic shifter has been fabricated in a 0.18-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS technology to demonstrate the feature of parallelly decoding multiple codewords. The performance analysis shows that when the number of small codewords is increased from 0 to 100000 per second, the throughput of the traditional QC-LDPC decoder drops from 844.80 Mbps to 4.40 Mbps, while the QC-LDPC decoder with the proposed segmented shifter only slightly drops to 814.01 Mbps. By applying the segmented QC-LDPC decoder in 5G base stations, the base stations are enabled to support more low-traffic users.

Experimental investigation of the embedded micro-channel manifold cooling for power chips

Power chips with high power dissipation and high heat flux have caused serious thermal management problems. Traditional indirect cooling technologies could not satisfy the increasing heat dissipation requirements. The embedded cooling directly inside the chip is the hot spot of the current research, which bears greater cooling potential comparatively, due to the shortened heat transfer path and decreased thermal resistance. In this study, the thermal behaviors of the power chips were demonstrated using a thermal test chip, which was etched with micro-channels on its substrate?s backside and bonded with a manifold which also fabricated with silicon wafer. The chip has normal thermal test function and embedded cooling function at the same time, and its size is 7 ? 7 ? 1.125 mm3. This paper mainly discussed the influence of width of micro-channels and the number of manifold channels on the thermal and hydraulic performance of the embedded cooling structure in the single-phase regime. Compared with the conventional straight micro-channel structure, the cooling coefficient of performance of the 8 ? ?50 (number of manifold distribution channels: 8, micro-channel width: 50 ?m) structure is 3.38 times higher. It is verified that the 8 ? ?50 structure is capable of removing power dissipation of 300 W (heat flux: 1200 W/cm2) at a maximum junction temperature of 69.6? with pressure drop of less than 90.8 kPa. This study is beneficial to promote the embedded cooling research, which could enable the further release of the power chips performance limited by the dissipated heat.

Literature review on the experimental method and interpretation of the edge chipping test (ECT)

Literature review on the experimental method and interpretation of the edge chipping test (ECT)