Chemical Mechanical Polishing Step Research Articles

(Invited) Novel Brush Design for Post CMP Cleans

Chemical Mechanical Polishing (CMP) process is one of the key processes in semiconductor wafer processing. A sub 10nm wafer fabrication process may require more than 40 dielectric and metal CMP steps. As CMP process requirements get more stringent, CMP slurries are formulated with smaller and smaller metal oxide abrasive particles. The abrasive particles may also be surface modified or doped with other metal oxides. Post CMP cleaning chemistry formulations are designed to remove polish byproducts, pad residues and abrasive particles from wafer surface. Chemical composition and PH are tuned for modulating wafer surface-particle interactions so brushes can mechanically “sweep” them off the surface. PVA brushes, used of post CMP cleans, are a highly porous network of crosslinked polyvinyl acetate with pore size in the range of 30 – 100 um and 80% - 90% porosity, depending on the type of brush being used. While PVA brushes have largely met the process capability requirements, they have limitations for advanced cleans such as nano-particle removal. As CMP process continues to expand to new dielectric and metal films for different process steps in wafer fabrication, there is a need for customized brush material and surface design for optimal cleaning efficiency.We discuss a new engineered post CMP brush design that shows high efficiency in nano-particle cleans and allows high level of material tunability. New brush design is an engineered composite with an open cell microporous core, overlaid with engineered fibers in form of loops. Brush design is compatible with existing post CMP cleans. Figure 1(a) shows the new design, where in DIW enters the brush through the center of microporous core and flows outwards to the surface. As water exits the surface, it flows over and across the loops and contacts the wafer surface. Flow resistance through core and loops can be independently tuned, which allows better fluid distribution and more effective cleans. Figure 1(b) show a close-up schematic of interaction between loop and particle. Flexing of the loops on brush surface provides improved contact as well as cleaning ability Brush design can be optimized for chemical and mechanical properties with choice of fiber material, fiber diameter and loop height. Figure 2 shows the Zeta potential of PVA and different loop materials. The fiber material maybe selected such that zeta potential of the loops can enhance mechanical action in removing particle. Mechanical action of the Loops can be modeled as a cantilever and force on the particle is exerted by flexing of the loops.Deflection of loops can be approximated with flexure stiffness of rods with point load at free end. For initial purposed loop is approximated as single element. The equation can be rewritten to calculate cleaning force P at the free end for given loop deflection (Y), P = 3EIY/L3 (1)Where E is elastic modulus, I = moment, L = length of fiber and for rod shapes; I = Pi*(r4/4)The adhesion of particles on the surface is due to the effect of van der Waals and electrostatic forces. The total adhesion force on the surface can be written as: F=F vdw + F edl (2) where Ft is total adhesion force, Fvdw is the van der Waals force, and Fedl is the electrostatic force.Fvdw = AR/6r2 (3)Where A is the Hamaker constant, R is particle radius, r is the separation distanceFor effective removal of particles, P >/= F (4)Flex force and adhesion force were modeled based on equation (1) and (3) and are shown in Figure 3. New brush design was used for post CMP cleaning of silicon dioxide wafers polished with ceria slurry. Two different brush designs were tested for cleaning efficiency. Modeling data and comparison with experimental results is presented. Figure 1

A Dry Etch Approach To Reduce Roughness and Eliminate Visible Grind Marks in Silicon Wafers Post Back-Grind

3D wafer packaging represents a significant component of the total wafer level processing cost. Replacement of the Chemical Mechanical Polishing (CMP) process step with a corresponding dry etch can yield significant time and cost savings. Incorporating equipment already utilized in the 3D integrated wafer packaging process during the subsequent Through Silicon Via (TSV) reveal step, process efficiencies can be achieved, with overall die yields being maintained. Using dry etch technology to treat a 200nm rough back-ground silicon surface, a smooth surface with a peak to valley roughness of less than 6nm is demonstrated. This patented process differs from other dry etch smoothing techniques in that it aims to eliminate any visual grind marks rather than just reducing the surface roughness. The elimination of visible grind marks is critical in later optical inspection where they are falsely identified as defects. The quality of the surface is equivalent to that of a CMP processed wafer and as such, this process has been implemented in manufacturing replacing the CMP step. The novel process described combines a surface modification followed by a roughness reduction in an iterative manner to produce a smooth surface without visible grind marks post processing.

An Introduction to Metal and Via Fill

In VLSI manufacturing, certain steps such as Chemical Mechanical Polishing (CMP) could affect the functioning of the chip thereby affecting yield. The fill flow adds additional metal and via features to the layout so that the density of metal and vias are uniform across the layout. When metal and vias are uniformly spread across the layout, the side effects of the chemical mechanical polishing step are minimized because variation in polishing depth is minimized. Since the fill process involves addition of metal and via features to the finished layout, this could affect critical layout metrics such as timing. Therefore, it is best if the layout synthesis flow i.e. the place and route flow is made fill-aware to improve performance predictability and enable faster layout convergence. In this paper, we provide a brief overview of the fill problem, algorithms to analyze density and fill synthesis.

(Invited) Nm-Scale Patterns and Selectivity: A Blessing or a Curse

Area-selective deposition (ASD) is a promising technique for semiconductor device manufacturing. The replication of nanoscale patterns by ASD can simplify device fabrication process flows by reducing the number of lithography, etch and chemical-mechanical polishing steps. In addition, ASD could eliminate pattern overlay errors. ASD is of special interest as device dimensions scale and has recently been shown as viable approach for the fully self-aligned via, to enable interconnect scaling beyond the 3 nm node [1]. However, the dependence of the selectivity of ALD and CVD processes on the patterning process and pattern dimensions is poorly documented. This aspect will be investigated in the current presentation. We will discuss the fundamental mechanisms of ALD growth mechanisms and how they influence selectivity. Next, we will discuss an example of Ru ASD with defect mitigation in nm-scale patterns on full 300-mm wafers [2].[1] Chen et al., IEDM21, 486-489.[2] Clerix et al., Adv. Mater. Interfaces 2021, 2100846.

Origins of wear-induced tungsten corrosion defects in semiconductor manufacturing during tungsten chemical mechanical polishing

During chemical mechanical polishing (CMP) process optimization, a unique corrosion defect was identified in the tungsten (W) contact plugs, which were investigated to develop practical solutions to improve CMP mass productivity. The corrosion defect occurred in the absence of external incident energy and was observed to occur only at the W plugs connected to the P+/n-well close to the wafer edge. To examine the root cause of the corrosion, a series of experiments was carried out at each W CMP step, using in-line defect inspection. Additional experiments were conducted using on-line inductively coupled plasma mass spectrometry (ICP-MS) to understand pH- and potential-dependent electrochemical dissolution behaviors of W. Experimentally, W corrosion was confirmed to be exacerbated if the surface oxide of the W plugs is removed by the deionized water (DIW) rinsing step under wafer pressurization, then exposed to DIW and alkaline cleaning solution. Although the DIW rinsing step is commonly performed to clean polishing pads right after the main polishing, a small amount of applied pressure (0.5 psi) without slurry supply can lead to corrosion defects. This wear-induced corrosion of the W plugs can be prevented by removing the applied pressure during the post DIW rinsing step of W CMP.

Defect Distribution in Doped Silicon Nanostructures Characterized By Means of Scanning Spreading Resistance Microscopy

Scanning Spreading Resistance Microscopy (SSRM) is a well-known technique for electrical characterization of dopant distributions in semiconductors. The resistance between a conductive atomic force microscope (AFM) tip and a large area contact on a semiconductor sample gives direct hint of sample resistivity underneath the tip. The sample surface has to be polished to achieve a smooth surface which is crucial for a low ohmic electrical contact between tip and sample. In theory, the formula of spreading resistance Rspr = ρ/4a with tip radius a connects SSRM raw data to resistivity data which can be transformed to concentration data of corresponding dopants. In experiment, additional series resistances and electrical defects have an impact on the SSRM analysis so that the formula does not hold any more. A SSRM scan on a calibration sample with regions of different well-known dopant concentrations enables an empirical relationship between R and ρ. This relationship is only valid for the specific defect distribution and tip-sample contact of the calibration sample. Both the defect distribution and the tip sample contact, respectively, depend strongly on sample preparation. Reliable calibration of unknown dopant distributions in semiconductor samples is only possible in the case of a perfectly reproducible sample preparation which is however hard to attain. Therefore, an accurate quantification of SSRM data remains difficult.One first step towards SSRM quantification requires an improved understanding and control of electrical defects on the sample surface which affect the SSRM measurement. In this work, we apply SSRM on well characterized n- and p-type dopant profiles in silicon bulk- and nanostructures. The deviation of the experimental SSRM data from simulated spreading resistance profiles provides direct information on type, quantity and origin of electrical defects in the sample.Our analysis of bulk samples reveals two type of preparation induced defects: n-type surface defects and hydrogen traps which deactivate boron atoms. The number of surface defects is proportional to the surface roughness. An improved sample preparation with additional polishing steps reduces the impact of this defect on the SSRM analysis. Hydrogen traps are driven into the sample during water based chemical mechanical polishing steps. An annealing of the sample at 250°C for 20 minutes reactivates most of the boron atoms.A third type of defect was noticed in nanostructured samples. Silicon nano pillars with diameters between 500 and 600 nm are manufactured in a top-down approach out of a silicon wafer with a 600 nm deep boron diffusion profile. Figure 1 shows the SSRM data of the bulk sample (a), the cross-sectional prepared nano pillar (b), and the depth profiles of SSRM analysis (c). The SSRM signal at the top of the pillar is dominated by the boron profile (b). The side walls are covered with gold as second contact for SSRM analysis. Obviously, the SSRM depth profile at the shell region (#2, circles) of the pillar is deeper than at the core (#3, triangles) and in the bulk sample (#1, squares) (c). The dopant distribution itself cannot vary across the pillar as the nanofabrication is done by dry-etching at cryogenic temperatures. We explain the variance in SSRM signal by acceptor defect states at the pillar shell which increase the number of p-type charge carriers in the shell region.COMSOL simulations of the SSRM analysis, including the impact of defects on the resistance profile, is used to quantify the defect distributions. The calculated resistance profiles accurately describe the experimental data (black dotted lines in (c)) and support our assumption on the distribution of electrical defects in silicon nanostructures. Figure 1

Chemical Mechanical Polishing and Direct Bonding of YAG

Current limitations in both single crystal and polycrystalline (ceramic) solid state laser technologies for high power applications stem from thermal effects that cause degradation in both lasing efficiency and beam quality. YAG and Y2O3 have favorable material properties for producing these high power lasers. We demonstrate chemical mechanical polishing (CMP) processes for YAG and Y2O3 resulting in smooth surfaces, (< 1 nm RMS roughness), defect free, and subsequently suitable for direct bonding. The CMP process has been used in conjunction with surface activation to form single crystal YAG-YAG and polycrystalline Y2O3-Y2O3 bonded elements showing a proof of concept for the fabrication of composite laser elements. YAG single crystals were successfully polished with a 70-nm colloidal silica solution containing NaOH (pH 9.9). X-ray photoelectron spectroscopy measurements provided insights to the chemical impact of the NaOH. After NaOH exposure, YAG showed complete removal of Al from tetrahedral sites and a change in the Y3/2 and Y5/2 peak area ratios, indicating that the surface of YAG was sufficiently modified to allow the silica particles to abrade the byproduct surface layer. The final surface roughness after polishing was measured at 0.1 nm RMS roughness with no scratches deeper than 0.3 nm. YAG single crystals were also polished with a 70-nm Al2O3 slurry containing NaOCl (pH 11.4), however AFM measurements showed that the surface produced, 0.5 nm RMS roughness with no scratches deeper than 6.0 nm, was not as good as polishing with the colloidal silica slurry which was attributed to the effect of the chemical action of NaOH with the YAG surface. Polishing polycrystalline Y2O3 required a slurry with less aggressive chemical reactions, so the NaOCl/Al2O3 slurry was used to successfully polish the substrates to RMS roughness values of 0.5 nm and scratches no deeper than 1.0 nm. Triple axis diffraction rocking curves and double crystal x-ray diffraction imaging were used to demonstrate that the CMP process also removed subsurface damage that was present in the as-supplied material. The triple axis technique was also successfully employed for the first time to demonstrate that the polycrystalline Y2O3 subsurface damage was also significant reduced after the CMP process. After CMP and surface treatment, YAG-YAG and Y2O3-Y2O3 were bonded together and annealed at 1425 °C with no applied pressure. Cross section and plan view high resolution transmission electron images of the YAG-YAG bonded interface revealed a defect free bonding interface. Light transmission measurements showed that 90% of the interface area was bonded at room temperature contact and was further strengthened with annealing at 1425 °C for 72 hours. These conditions possess a much lower thermal budget than those previously shown to be required to bond YAG without a CMP step. The CMP and surface treatment processes that have been developed are applicable towards the creation of solid state laser composite elements and enable further progress and development for high power laser applications.

Surface Engineering of SiC through Nanogrinding and CMP

Processing silicon carbide (SiC) wafers to achieve an epi-ready quality finish typically requires many lapping and a very long chemical mechanical polishing (CMP) steps. In this paper, we report the thinning down of 6” SiC wafers to sub-nanometer surface finish in less than two hours. Three process steps (rough grinding, nanogrinding and CMP) are involved. Rough grinding thins down the wafer with fast feed rate and maintain excellent flatness. Nanogrinding allows the surface finish to improve down to a few nanometers. The last CMP step provides high planarization efficiency. Overall the throughput of SiC processing is substantially increased over current market solutions.

Residual Stress and Pop-Out Simulation for TSVs and Contacts in Via-Middle Process

In the via-middle process of 3-D integrated circuit manufacturing, through-silicon via (TSV) annealing causes mechanical stress not only to its surrounding structures, including liner and landing pad, but also the contacts nearby. This process may result in a noticeable pop-out in TSVs and/or contacts, thus complicating the subsequent chemical mechanical polishing (CMP). In addition, residual stress may cause delamination or crack. In this paper, we conducted detailed simulations of the residual stress and pop-out mechanisms for TSVs and neighboring contacts. Our primary focus was on the interplay of TSV-induced and contact-induced stresses and their combined impact on pop-out height. In addition, we conducted a sensitivity analysis of key parameters, including distance, plasticity, annealing temperature, and the distribution of neighboring contacts. This paper showed that these parameters notably affect the stress and the pop-out of TSVs and contacts. This in turn is expected to complicate the subsequent CMP steps. Finally, we applied the linear superposition method to predict stress and validated its accuracy by comparing the results with finite element analysis simulation. The results of the comparison demonstrated that the superposition method was accurate. Therefore, it could be used to predict the stress for full-chip design.

Influence of Si wafer thinning processes on (sub)surface defects

Wafer-to-wafer three-dimensional (3D) integration with minimal Si thickness can produce interacting multiple devices with significantly scaled vertical interconnections. Realizing such a thin 3D structure, however, depends critically on the surface and subsurface of the remaining backside Si after the thinning processes. The Si (sub)surface after mechanical grinding has already been characterized fruitfully for a range of few dozen of μm. Here, we expand the characterization of Si (sub)surface to 5μm thickness after thinning process on dielectric bonded wafers. The subsurface defects and damage layer were investigated after grinding, chemical mechanical polishing (CMP), wet etching and plasma dry etching. The (sub)surface defects were characterized using transmission microscopy, atomic force microscopy, and positron annihilation spectroscopy. Although grinding provides the fastest removal rate of Si, the surface roughness was not compatible with subsequent processing. Furthermore, mechanical damage such as dislocations and amorphous Si cannot be reduced regardless of Si thickness and thin wafer handling systems. The CMP after grinding showed excellent performance to remove this grinding damage, even though the removal amount is 1μm. For the case of Si thinning towards 5μm using grinding and CMP, the (sub)surface is atomic scale of roughness without vacancy. For the case of grinding+dry etch, vacancy defects were detected in subsurface around 0.5–2μm. The finished surface after wet etch remains in the nm scale in the strain region. By inserting a CMP step in between grinding and dry etch it is possible to significantly reduce not only the roughness, but also the remaining vacancies at the subsurface. The surface of grinding+CMP+dry etching gives an equivalent mono vacancy result as to that of grinding+CMP. This combination of thinning processes allows development of extremely thin 3D integration devices with minimal roughness and vacancy surface.

OS0110 エリプソメトリ測定によるウェハー表面の粒子検出

In the chemical mechanical polishing step in semiconductor manufacturing process is a problem that the detection of residual contaminant particles on the substrate surface. Light scattering method using a laser for detection of contaminating residual particles are used. However, since the separation of micro-roughness and residual contaminant particles has become difficult for the light scattering method, we have focused on a spectroscopic ellipsometer. Spectroscopic ellipsometer is capable of non-contact, non-destructive, high-speed measurement. Also, it is possible to measure the structure of a very thin surface layer of the sub-nm. In the present study attempts to detection of a substrate on the nanoparticles by ellipsometry, we examined the usefulness of this technique.

Metal Flake Defect and Its Formation Mechanism during Replacement Metal Gate CMP Process

Replacement metal gate (RMG) has been introduced in semiconductor fabrication since 45 nm gate scaling era. RMG process has advantages in prevention of damage by gate etch and thermal process, and it gives work function material stability. Moreover, improvement of device performance is expected as well. Therefore it has been employed as industry standard process for advanced node transistor fabrication. However, the complexity of RMG process flow emphasizes the importance of metal gate chemical mechanical polishing (CMP) which plays a key role in the success of RMG formation. Three complementary CMP steps (gate poly-Si CMP, poly-Si open CMP, metal gate CMP) are involved in RMG formation and comprehensive understanding of interplay among these CMP steps is the key to achieve uniform gate height across the wafer. In addition to extremely tight control of final gate height, post metal gate CMP defects are one of the most critical parameters affecting device performance as well as yield. Among various kinds of defects, metal flakes are most serious defect which fails transistor function by providing gate leakage channel. This paper approaches both integrational and CMP process aspect to reveal the mechanism of metal flake formation.

Effect of Dissolved Oxygen on the Removal of BTA from Cu By Tetra Methyl Ammonium Hydroxide

In the fabrication of copper interconnects, chemical mechanical polishing (CMP) is used to remove excess copper and barrier layers. Because of its ability to form a protective layer, Benzotriazole (BTA) is used as Cu corrosion inhibitor during CMP as well as post-CMP cleaning [1, 2]. It is desirable to remove this protective layer between multiple copper deposition and CMP steps. Investigations on the removal of chemisorbed BTA by tetra methyl ammonium hydroxide (TMAH), hydroxylamine and organic acid have been reported [2-4]. These studies have used 0.1 wt % and lower concentration of BTA at natural pH ( < 7) or alkaline pH (11) to form adsorbed layers [3-5]. The effect of dissolved oxygen content on the adsorption of BTA and subsequent removal by TMAH is not yet reported. In this work, removal of BTA adsorbed on Cu at a pH value of ~10, which is close to the conditions that exist during barrier CMP, using a quartz crystal microbalance (QCM) technique. Since the study focussed only on the BTA removal, particles were not included in the test solution. A thin layer of Cu was first electrodeposited on Au electrodes of a quartz crystal in an electrolyte containing 10 mM CuSO4 and 100 mM H2SO4. The electrodeposition was carried out at – 150 mV vs. Ag/AgCl for 300 s. An SRS QCM-200 model quartz crystal microbalance (QCM) was used to monitor the changes in mass of the Cu coated crystal, during BTA adsorption and removal. A freshly prepared surface was used for each run. The dissolved oxygen level was controlled by bubbling either nitrogen or air before and during the experiments. During the adsorption and removal experiments, the temperature was maintained at 30 ± 0.1 °C using a circulating bath. After the completion of each experimental run, the Cu layer was stripped by maintaining the electrode at +600 mV vs.Ag/AgCl in the same solution. In the first part of investigation, a Cu sample was immersed in KOH solution of pH 10 without BTA for 200 s. After this conditioning time, the solution was switched to 1 wt% TMAH. The changes in the crystal resonance frequency were converted to changes in mass per unit area, using Sauerbrey equation as Δm = -17.67(ng/cm2/Hz) Δf and reported in Figure 1. Figure 1(a) shows that when air is bubbled in the KOH solution, the mass increases over time and this is probably due to the formation of oxides and hydroxides of Cu. Upon switching the solution to TMAH, the mass decreases and goes below the original value. This indicates that TMAH removes Cu oxides, hydroxides and Cu. When the sample is immersed in KOH solution with nitrogen bubbling, the mass remains relatively constant, but switching the solution to TMAH causes a reduction in mass. This confirms that TMAH etches bare Cu. In the second part of the investigation, a Cu sample was immersed in KOH solution of same pH but containing 0.1 wt% BTA for 200 sec. The results are presented in Figure 1 (b). The mass increases to roughly the same extent regardless of whether air or nitrogen is bubbled in the solution. When the solution was switched to aerated TMAH solution, the mass decreases rapidly indicating that BTA and possibly the oxides of Cu are removed. On the other hand, when nitrogen deaerated (nitrogen saturated) TMAH was used, the mass continues to increase suggesting that BTA is not removed. These results indicate that BTA adsorbed on oxide free Cu surface is not attacked by TMAH to the same extent as that adsorbed on oxide free surface.

Development of TSV Reveal Process Using Very Fine Si/Cu Grinding and Metal Contamination Removal

Three-dimensional integrated circuits (3D-ICs) using through silicon via (TSV) have been developed as an emerging technology that can lead to significant progress (1–4). Among various TSV processes, the via-middle process has potential for wide spread use because formation of small-sized TSVs is relatively easy in the via-middle process. However, TSV reveal process must be performed for electrical contact in the via-middle process. This TSV reveal process is important because it can influence the metal contamination and stacking yield of 3D-ICs. Conventionally, TSV reveal is performed by Si grinding and Si dry etching (5). A disadvantage of that method is the resultant TSV depth deviation, which can cause bonding failure during wafer/chip stacking. In (6), TSV leveling was performed by introducing a chemical mechanical polishing (CMP) step after deposition of the backside insulator. However, the revealed TSVs break during CMP step if they exceed a certain height. To overcome these problems, we developed a novel TSV reveal process comprising direct Si/Cu grinding and metal contamination removal (7,8). First, simultaneous grinding of Cu and Si was performed using a novel vitrified grinding wheel. In situ cleaning with a high-pressure micro jet and the inelastic porous structure of the grinding wheel suppressed the adhesion of Cu contaminants to the Si, and TSVs were leveled and exposed. Next, an electroless Ni-B film was deposited on the Cu surface of the TSVs. The Si was etched with an alkaline solution, whereas the Cu was protected by the Ni-B film. An insulator was deposited, and then the insulator on the top surface of the TSV was removed. We achieved the backside reveal of TSVs without TSV depth deviation and suppressed Cu contamination to less than 1e11 atoms/cm2. However, after direct Si/Cu grinding with an 8000 grit grinding wheel, the average surface roughness of Si was 5–10 nm, which is larger than that after chemical mechanical polishing (CMP). In this paper, we developed vitrified grinding wheels with very high grit numbers (#30,000 and #45,000) and present an improved version of our TSV reveal process. The average surface roughness of Si after Si/Cu grinding was approximately 3 nm for the 30,000 grit grinding wheel and 1 nm for the 45,000 grit grinding wheel. This value is equivalent to that after CMP. The improved process produced a uniform reveal of 4-um-diameter TSVs without TSV depth deviation and Cu contamination. The Cu contaminant concentration on Si region between TSVs was small (&amp;lt;3e10 atoms/cm2). This process will reduce the cost of the TSV reveal process and considerably improve the TSV yield.

Low Cost and High Performance CMP Solution for Si Polishing in Backside Illumination (BSI) Application

Backside illumination (BSI) is an uprising technology to achieve high performance of CMOS (Complementary Metal-Oxide Semiconductor) imaging. Si CMP (Chemical-Mechanical Polishing) process is required in BSI application to remove grinding masks and dislocations from bonded wafer with typical 1.0~3.0um removal amount. BSI CMP appears easy compared to traditional IC CMP in that there is much less integration requirements from pre/post CMP steps. The challenges lie in CMP profile control to compensate incoming thickness variation from grinding for low TTV (total thickness variation), low surface roughness and supreme surface quality for optical path, and low cost for mass production. There is a need to develop slurries/process to conquer all the challenges. Reported in this paper is our recent effort to address such challenges in Si CMP process for BSI application by combining CMP slurry selection and process optimization together. The performances of these approaches were tested on laboratory-scale instruments and further optimized on 8” and 12” CMP tools. Polishing results from both blanket Si (EPI) wafers and SOI wafers are discussed to set up the final process conditions.

Smart-cut layer transfer of single-crystal SiC using spin-on-glass

The authors demonstrate “smart-cut”-type layer transfer of single-crystal silicon carbide (SiC) by using spin-on-glass (SoG) as an adhesion layer. Using SoG as an adhesion layer is desirable because it can planarize the surface, facilitate an initial low temperature bond, and withstand the thermal stresses at high temperature where layer splitting occurs (800–900 °C). With SoG, the bonding of wafers with a relatively large surface roughness of 7.5–12.5 Å rms can be achieved. This compares favorably to direct (fusion) wafer bonding, which usually requires extremely low roughness (&amp;lt;2 Å rms), typically achieved using chemical mechanical polishing (CMP) after implantation. The higher roughness tolerance of the SoG layer transfer removes the need for the CMP step, making the process more reliable and affordable for expensive materials like SiC. To demonstrate the reliability of the smart-cut layer transfer using SoG, we successfully fabricated a number of suspended MEMS structures using this technology.

Investigation of cleaning solution composed of citric acid and 5-aminotetrazole

In a damascene process for a copper metallization, the planarization method based on a chemical mechanical polishing (CMP) has been used for multilevel metallization. Although a buffing step was adopted in this CMP process, numerous residual abrasives, capable of increasing the resistance of copper lines, still existed after the second CMP step. For this reason, more research has focused on identification of an effective cleaning solution. We investigated a new cleaning solution consisting of citric acid and 5-aminotetrazole (ATRA) as a complexing agent and corrosion inhibitor, respectively. The citric acid was added to achieve a lift-off effect by removing the underlying copper oxide layer, whereas the ATRA was adopted to prevent abrasive re-adsorption by forming a passivation layer on the copper surface. The cleaning solution consisting of 0.006 M citric acid and 0.006 M ATRA displayed a particle density of 0.07 #/μm2 in an immersion test, and no particles were observed on a 4 cm2 coupon wafer in a real process test at pH 12.

Fabrication of Capacitive Micromachined Ultrasonic Transducers via Local Oxidation and Direct Wafer Bonding

We present the successful fabrication of capacitive micromachined ultrasonic transducers (CMUTs) with an improved insulation layer structure. The goal is to improve device reliability (electrical breakdown) and device performance (reduced parasitic capacitance). The fabrication is based on consecutive thermal oxidation steps, on local oxidation of silicon (LOCOS), and on direct wafer bonding. No chemical-mechanical polishing step is required during the device fabrication. Aside from the advantages associated with direct wafer bonding for CMUT fabrication (simple fabrication, cell shape flexibility, wide gap height range, good uniformity, well-known material properties of single-crystal materials, and low intrinsic stress), the main vertical dimension (electrode separation) is determined by thermal oxidation only, which provides excellent vertical tolerance control ( <;10 nm) and unprecedented uniformity across the wafer. Thus, we successfully fabricated CMUTs with gap heights as small as 40 nm with a uniformity of ±2 nm over the entire wafer. This paper demonstrates that reliable parallel-plate electrostatic actuators and sensors with gap heights in the tens of nanometer range can be realized via consecutive thermal oxidation steps, LOCOS, and direct wafer bonding without chemical-mechanical polishing steps.

Surface Interaction of Barrier Slurry Formulation Additives during Post Chemical Mechanical Polishing (CMP)

As today's leading edge manufacturers are developing and preparing to implement 22 nm technology node integrated circuits and beyond into manufacturing, new issues emerge. Certain components used in current generation CMP barrier slurries or new components used to achieve improved performance at the advanced nodes either no longer are sufficient or cause new integration issues. Many of these issues involve the surface state of the polished films after the Cu-barrier CMP step. Surface states during polishing can lead to undesirable topography effects, such as "fangs". Unprotected high density Cu lines can lead to high electrical leakage issues due to corrosion. Thin residual layers left behind on the polished surfaces can create defectivity or downstream deposition and/or contamination issues. This study looks closely at various formulation components used in barrier CMP slurries, how they electrochemically interact with the materials they contact and how they may change the post CMP polished surfaces.

Integration and electrical characterization of carbon nanotube via interconnects

Carbon nanotubes (CNTs) are considered a promising material for interconnects in the future generations of microchips because of their low electrical resistance and excellent mechanical stability. In particular, CNT-based contacts appear advantageous when compared with current tungsten or copper technologies and could therefore find an application as metal contacts interconnecting the transistors with the back end of line of the microchip. In this work, the integration of vertical CNT bundles in sub-micron contact holes is evaluated at wafer scale and the major integration challenges encountered in the practical realization of the process are discussed. Nickel PVD films were used to selectively grow CNT into the contact holes at temperatures as low as 400 °C, which is the thermal budget available for contacts. The height of the contacts and the length of the CNT are controlled by a chemical mechanical polishing step (CMP) after embedding the CNT into SiO 2. Ti/Au metal pads are then formed onto the CNT bundles by PVD and lift-off. The integrated CNT are electrically characterized and an annealing treatment was found to improve the CNT-via resistance. As the electrical properties of the CNT can be evaluated, the structure and the process presented constitute a test vehicle for the development of high-quality CNT-contacts.