Low Cost and High Performance CMP Solution for Si Polishing in Backside Illumination (BSI) Application

Abstract

Backside illumination (BSI) is an uprising technology to achieve high performance of CMOS (Complementary Metal-Oxide Semiconductor) imaging. Si CMP (Chemical-Mechanical Polishing) process is required in BSI application to remove grinding masks and dislocations from bonded wafer with typical 1.0~3.0um removal amount. BSI CMP appears easy compared to traditional IC CMP in that there is much less integration requirements from pre/post CMP steps. The challenges lie in CMP profile control to compensate incoming thickness variation from grinding for low TTV (total thickness variation), low surface roughness and supreme surface quality for optical path, and low cost for mass production. There is a need to develop slurries/process to conquer all the challenges. Reported in this paper is our recent effort to address such challenges in Si CMP process for BSI application by combining CMP slurry selection and process optimization together. The performances of these approaches were tested on laboratory-scale instruments and further optimized on 8” and 12” CMP tools. Polishing results from both blanket Si (EPI) wafers and SOI wafers are discussed to set up the final process conditions.