Abstract
Carbon nanotubes (CNTs) are considered a promising material for interconnects in the future generations of microchips because of their low electrical resistance and excellent mechanical stability. In particular, CNT-based contacts appear advantageous when compared with current tungsten or copper technologies and could therefore find an application as metal contacts interconnecting the transistors with the back end of line of the microchip. In this work, the integration of vertical CNT bundles in sub-micron contact holes is evaluated at wafer scale and the major integration challenges encountered in the practical realization of the process are discussed. Nickel PVD films were used to selectively grow CNT into the contact holes at temperatures as low as 400 °C, which is the thermal budget available for contacts. The height of the contacts and the length of the CNT are controlled by a chemical mechanical polishing step (CMP) after embedding the CNT into SiO 2. Ti/Au metal pads are then formed onto the CNT bundles by PVD and lift-off. The integrated CNT are electrically characterized and an annealing treatment was found to improve the CNT-via resistance. As the electrical properties of the CNT can be evaluated, the structure and the process presented constitute a test vehicle for the development of high-quality CNT-contacts.
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