An Introduction to Metal and Via Fill

Abstract

In VLSI manufacturing, certain steps such as Chemical Mechanical Polishing (CMP) could affect the functioning of the chip thereby affecting yield. The fill flow adds additional metal and via features to the layout so that the density of metal and vias are uniform across the layout. When metal and vias are uniformly spread across the layout, the side effects of the chemical mechanical polishing step are minimized because variation in polishing depth is minimized. Since the fill process involves addition of metal and via features to the finished layout, this could affect critical layout metrics such as timing. Therefore, it is best if the layout synthesis flow i.e. the place and route flow is made fill-aware to improve performance predictability and enable faster layout convergence. In this paper, we provide a brief overview of the fill problem, algorithms to analyze density and fill synthesis.