Hotspot detection and removal flow using multi-level silicon-calibrated CMP models

Abstract

As we move to advanced technology nodes, the requirements on within chip and across wafer planarity are becoming more demanding [1]. Also, the number of Chemical Mechanical Polishing (CMP) processes and steps used in microelectronic chip manufacturing is increasing rapidly, in an effort to meet the stringent planarity requirements [1]. However, the complex pattern dependencies inherent in CMP processes, and the cumulative nature of the topography generated by these processes make it challenging to meet the aforementioned stringent uniformity requirements for the variety of designs produced. Consequently, we expect to see an increased CMP and related hotspots on advanced node designs. Accurately detecting CMP and related hotspots (such as pooling, DOF hotspots, topography variation hotspots etc.) and providing guidelines to fix or prevent them is therefore critical for CMP process development, yield ramp up and shorter design and manufacturing cycles. In this paper we present a hotspot detection and removal/prevention flow. The flow uses Cadence Design System’s manufacturing modeling methodology that predicts feature scale, within chip, and wafer level topography. The modeling methodology takes into account etch depth, deposition, and CMP variations across multiple levels in the design, and across multiple process steps within a given design level.