Characteristics Of Tunneling Field-effect Transistors Research Articles

Design and Development of Biosensors Based on Nano Tube Tunnel Field Effect Transistor

Tunnel Field Effect Transistor (TFET) is gaining recognition and provide solution for Integrated Circuit (IC) design with low power. This is due to TFET's carrier transportation scheme, which utilizes inter-band tunneling of carriers, and its fabrication similarity to MOSFET. TFET presents itself as a widely adopted device structure that can overcome the limitations of MOSFETs. However, TFETs suffer from poor DC and Radio Frequency (RF) performance, mainlydue to minority carrier transport and physical doping, which forms an abrupt junction in nanoscale devices due to RDFs. The junction-less device structure presents a viable solution to these issues without sacrificing DC parameters, even at high-frequency. Furthermore, the nanotube structure of TFET effectively reduces the Subthreshold Swing (SS) and leakage current due to better controllability of channel. The gate-all-around structure of nanotube TFET improves the surface potential distribution over the channel region, not only enhancing the DC characteristics of TFET but also improving the high-frequency parameters. The core gate Nano Tube (NT)-TFET is a promising device structure for exploring its application in the field of biomedical science as a biosensor. The proposed core gate nanotube structure provides a larger surface area for immobilizing biomolecules in the cavity, thus improving sensitivity analysis. This work proposes the utility of a novel core gate NT-TFET as a biosensor for detecting label-free biomolecules and DNAs. In this design, the detection capability of biosensor is improved, and the detection processes are investigated by high-frequency parameters of the proposed twin cavity dual metal NT-TFET biosensor. This study demonstrates the sensitivity analysis of biosensor based on transit time and device efficiency, which are two critical high-frequency parameters. This approach results in a biosensor with a lower annealing budget, making it more cost-effective and with comparatively highersensitivity

Effects of Pillar Conditions on DC/AC Characteristics of Tunnel Field-effect Transistor with Vertical Structures

To investigate the effects of various pillar conditions such as pillar thickness (T<SUB>pillar</SUB>), pillar height (T<SUB>Si</SUB>), and doping concentration of pillar on DC characteristics of TFETs with vertical structures (TFET<SUB>VS</SUB>) and AC switching characteristics of TFET<SUB>VS</SUB> inverters, Mixed-mode device and circuit TCAD simulations are performed. As 1) the T<SUB>pillar</SUB> is thicker, 2) the T<SUB>Si</SUB> is increased, and 3) the doping concentration of the pillar is reduced, the tunneling current between source and channel gets increased and the gate-to-drain capacitance (C<SUB>GD</SUB>)-gate voltage (V<SUB>G</SUB>) curve becomes positive-shifted due to the weaker controllability of V<SUB>G</SUB> on the drain-side channel. Through the transient responses of TFET<SUB>VS</SUB> inverters with various pillar conditions, it is revealed that AC switching performance can be improved by the enhanced tunneling current and the positive-shifted C<SUB>GD</SUB>-V<SUB>G</SUB> curve caused by the weaker V<SUB>G</SUB> controllability on the drain-side channel.

Implementation of Boolean Functions Using Tunnel Field-Effect Transistors

Tunnel field-effect transistors (TFETs) are being examined as a possible replacement of MOSFETs for digital applications. However, TFETs have small ON-state current and, typically, exhibit reduced speed compared with conventional MOSFETs. Nevertheless, TFETs have some distinct characteristics that can be exploited for digital applications. In this article, using simulations, we show that a single device, in which two terminals are biased independently, can realize all primary two-input Boolean functions, such as AND, OR, NAND, NOR, XOR, and XNOR. By modifying the architecture of double-gate TFET (DGTFET) slightly and appropriately choosing device parameters, the Boolean functions AND, OR, NAND, NOR, and XNOR can be implemented. In addition, we propose a twin double-gate (TDG) TFET architecture, which can implement the inhibition functions $A'B$ and $AB'$ . By suitably combining the inhibition functions, an XOR functionality can be obtained in a single device. These implementations demonstrate that the unique characteristics of TFET, such as ambipolar conduction and dependence of tunneling on the gate–source/drain overlaps, can be exploited to realize logic functions compactly.

Photosensor Based on Split Gate TMD TFET Using Photogating Effect for Visible Light Detection

This paper reports a highly-sensitive and low power photosensor based on split gate tunnel field effect transistor (TFET) structure for visible light detection in wavelength ranging from 450-750 nm. The TFET based sensing device utilizes the photogating effect in a portion of transition metal dichalcogenide (TMD) channel. The optically tunable workfunction contrast between the two gates of dual material gate (DMG) TFET achieves significant gains in the overall device characteristics. It demonstrates high photo-to-dark current ratio of the order of 10 8 and variation in responsivity in the range between 10 3 AmW -1 to 10 -5 AmW -1 for V gs = -0.9 V. This paper further discusses the photodetector performance based on the position of the photogate on the tunneling or auxiliary side, the gate splitting ratio between the photosensing region and the metal, and the n-TFET based device design. The device performance has been analyzed using the analytical model for the optically controlled workfunction. This hybrid device consisting of an ultrathin channel sensitized with absorbing semiconductors while exploiting the characteristics of TFET leads to a new generation of highly sensitive photodetectors.

Methodology to Investigate Impact of Grain Orientation on Threshold Voltage and Current Variability in Tunneling Field-Effect Transistors

In this article, an investigation has been performed to statistically analyze the entire subthreshold characteristics of tunnel field-effect transistor (TFET) depending on a gate work function variation (WFV). Firstly, the current variations are evaluated through turn-on voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> ) and threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) with help of technology computer-aided design (TCAD) simulation. Secondly, the variation of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> are quantitatively analyzed by coefficient of determination (R <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) in the regression analysis. The R <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> values are extracted according to the divided the gate prats. Finally, it is confirmed that the WFV of the gate parts causes the current variation in areas where tunneling is varied mainly according to the gate bias.

Device physics and design of hetero-gate dielectric tunnel field-effect transistors with different low/high-k EOT ratios

The hetero-gate dielectric (HGD) structure was recently experimentally demonstrated to enhance the electrical performance of tunnel field-effect transistors (TFETs). This study examined the mechanisms underlying the HGD structure functioning and investigated the design of the structure to enhance the electrical characteristics of TFETs with different ratios of low- and high-k equivalent oxide thicknesses (EOT). The on-current enhancement by the source-side dielectric heterojunction, which directly modulates the on-state tunnel width, was much larger than that by the drain-side dielectric heterojunction, which indirectly affects the on-current by modulating the subthreshold tunnel width. The subthreshold swing is improved by the formation of a conduction band well near the source-channel junction. However, the swing improvement is limited by the hump effect when this local potential well approaches the source. The optimal design of the HGD structure and the maximal enhancement of on-current considerably depend on the EOT ratio of low- and high-k dielectrics. The on-current is most enhanced by the optimized HGD structure at a low/high-k EOT ratio of ten times, that is, approximately 160% of the on-current of the uniform high-k TFET counterpart. Due to the continuous trend of increasing the k-values or scaling EOTs, understanding the dependence of device physics and design on the low/high-k EOT ratio is crucial to optimize the performance of HGD-TFETs.

Investigation of Positive Bias Temperature Instability Characteristics of Fully Depleted Silicon on Insulator Tunneling Field Effect Transistor with High-k Dielectric Gate Stacks.

The positive bias temperature instability (PBTI) characteristics of fully depleted silicon on insulator (FD-SOI) tunneling field effect transistor (TFET) are investigated in comparison with those of metal oxide semiconductor field effect transistor (MOSFET) fabricated with the same technology process. Unlike some of the previously reported studies, in which the PBTI lifetime of TFET is much longer than that of MOSFET, in this study, the PBTI lifetime of TFET is found to be shorter than that of MOSFET. This result is very interesting, because degradation of electrical parameters of TFET is mainly affected by local traps near the source junction rather than global traps in the channel region. Large degradation of the electrical parameters of TFET due to PBTI stress would result from large fluctuation of the vertical electric field caused by traps near the source junction. This electric field fluctuation near the local region in TFET has more impact on electrical parameter degradation than channel conductivity fluctuation in MOSFET. Therefore, to improve the reliability characteristics of TFET, evaluation of PBTI characteristics and improvement of the quality of gate oxide near the source junction are essential.

Bilayer tunneling field effect transistor with oxide-semiconductor and group-IV semiconductor hetero junction: Simulation analysis of electrical characteristics

Operation mechanisms and electrical characteristics of tunneling field-effect transistors (TFETs) employing a hetero tunneling junction by utilizing an n-type oxide-semiconductor (OS) and a p-type group-IV-semiconductor are comprehensibly analyzed. Gate-normal band-to-band tunneling (BTBT) has high potential for the superior TFET performance such as high on-state current and small sub-threshold swing (S.S.). Additionally, a hetero tunneling junction with type-II energy band alignment is promising to exponentially increase tunneling probability with keeping small off-state current. Therefore, in this study, we investigate the impact of key material and device parameters such as energy band alignment of source/channel regions and thickness of the OS channel layer or gate insulator based on technology computer aided design (TCAD) simulation. The gate-controlled uniform band bending along the source-drain direction realizes uniform BTBT in the entire region of the hetero tunneling junction. Also, the reduction of the tunneling barrier height, which is continuously controlled by the conduction band minimum of the OS-channel and the valence band maximum of the IV-source, is effective to increases on-state current and decrease S.S. value. On the other hand, the thicknesses of OS channel layer and gate insulator have strong influences on tunneling probability and threshold voltage. Therefore, the sub-threshold characteristics of TFETs are sensitive to non-uniformities in the tunneling junction such as channel thickness fluctuation and surface potential fluctuation at the metal-oxide-semiconductor (MOS) interfaces. These numerical analyses of the device operation are essentially important to understand the effects of key device parameters on the TFET performance and to realize the superior electrical performance.

Influence of impurity concentration in Ge sources on electrical properties of Ge/Si hetero-junction tunneling field-effect transistors

We have experimentally demonstrated that there is the optimum B doping concentration in the Ge source in terms of the electric performance of Ge/Si hetero-junction tunneling field-effect transistors (TFETs). The degradation in subthreshold swing (SS) is observed for TFETs with the source B concentration higher than 1 × 1020 cm−3, which can cause the degeneration in Ge. This source concentration dependence can be explained by the depression of the energy filtering effect due to the degeneracy of the Fermi level (EF). This interpretation is supported by the temperature dependence of SS in the Ge/Si TFETs with different source concentrations. Also, a low SS value of 60.6 mV/dec, an Ion value of 82.3 nA/μm, and a large Ion/Ioff ratio of 6.8 × 106 are obtained for the 1.1% tensile strain channel with the optimized B concentration in the Ge source. It is found that the influence of the source EF on the electrical characteristics of TFETs is more pronounced for the strained-Si channel TFETs with smaller Eg.eff.

Numerical analysis of band tails in nanowires and their effects on the performance of tunneling field-effect transistors

Band tails in heavily doped semiconductors are one of the important parameters that determine transfer characteristics of tunneling field-effect transistors. In this study, doping concentration and doing profile dependences of band tails in heavily doped Si nanowires were analyzed by a nonequilibrium Green function method. From the calculated band tails, transfer characteristics of nanowire tunnel field-effect transistors were numerically analyzed by Wentzel–Kramer–Brillouin approximation with exponential barriers. The calculated transfer characteristics demonstrate that the band tails induced by dopants degrade the subthreshold slopes of Si nanowires from 5 to 56 mV/dec in the worst case. On the other hand, surface doping leads to a high drain current while maintaining a small subthreshold slope.

Nano-scale Transistors with Circuit Interaction for Designing Energy-Efficient and Reliable Adder Cells at Low VDD

ABSTRACTDesigning reliable and energy-efficient circuits with CMOS technology scaling is a pressing challenge at scaled supply voltages. This paper provides design insights and circuit interaction approach with two such emerging devices, double-gate FinFETs and tunnel field effect transistors (TFETs), for designing basic computing building blocks such as adder cells. At the circuit level, TFET-based transmission gate logic 1-bit full adder (TGLA) and improved transmission gate logic 1-bit full adder (ITGLA) cells have been proposed and designed taking into unidirectional conduction and ambipolar currents of TFETs into consideration. The performance of TFET designs has been benchmarked with 20 nm double-gate Si FinFET technology. ITGLA design is a better energy-efficient option in comparison to TGLA design with FinFETs but has reduced reliability. It has been demonstrated that the steep slope characteristics of TFETs enable both TGLA and ITGLA designs to display improved energy efficiency and reliability characteristics (in the form of reduced overshoot, reduced glitches, improved logic swing, etc.). These characteristics make TFETs desirable candidates for reliable and energy-efficient computing architectures at scaled supply voltages.

Insights Into Tunnel FET-Based Charge Pumps and Rectifiers for Energy Harvesting Applications

In this paper, the electrical characteristics of tunnel field-effect transistor (TFET) devices are explored for energy harvesting front-end circuits with ultralow power consumption. Compared with conventional thermionic technologies, the improved electrical characteristics of TFET devices are expected to increase the power conversion efficiency of front-end charge pumps and rectifiers powered at sub- $\mu \text{W}$ power levels. However, under reverse bias conditions the TFET device presents particular electrical characteristics due to its different carrier injection mechanism. In this paper, it is shown that reverse losses in TFET-based circuits can be attenuated by changing the gate-to-source voltage of reverse-biased TFETs. Therefore, in order to take full advantage of the TFETs in front-end energy harvesting circuits, different circuit approaches are required. In this paper, we propose and discuss different topologies for TFET-based charge pumps and rectifiers for energy harvesting applications.

Study of gate leakage current paths in p-channel tunnel field-effect transistor by current separation measurement and device simulation

Scaling the gate dielectric is a key to improving the steep switching characteristics of tunnel field-effect transistors (TFETs). The effect of the gate leakage current caused by this scaling has not fully been investigated until now. In this work, gate leakage current paths in a p-channel TFET are experimentally investigated by designing three types of measurement setup for separating the current paths. Our measurements reveal that the so-called gate-edge leakage current that directly flows from the gate into the source adversely affects the subthreshold characteristics of the source current. We also report that the areal leakage current tunneling from the gate to the channel causes the OFF current to increase. A device simulation is performed to separate the contribution of electron gate tunneling from that of hole gate tunneling and to understand the mechanism underlying these tunnelings, which reveals that electron tunneling occurring in the nanometer-scale source–gate overlap determines the gate leakage. Structural engineering around the source–channel overlap plays an important role in achieving high-performance TFETs.

Universal analytic model for tunnel FET circuit simulation

A simple analytic model based on the Kane–Sze formula is used to describe the current–voltage characteristics of tunnel field-effect transistors (TFETs). This model captures the unique features of the TFET including the decrease in subthreshold swing with drain current and the superlinear onset of the output characteristic. The model also captures the ambipolar current characteristic at negative gate–source bias and the negative differential resistance for negative drain–source biases. A simple empirical capacitance model is also included to enable circuit simulation. The model has fairly general validity and is not specific to a particular TFET geometry. Good agreement is shown with published atomistic simulations of an InAs double-gate TFET with gate perpendicular to the tunnel junction and with numerical simulations of a broken-gap AlGaSb/InAs TFET with gate in parallel with the tunnel junction.

Impact of Interface Traps on Direct and Alternating Current in Tunneling Field-Effect Transistors

We demonstrate the impact of semiconductor/oxide interface traps (ITs) on the DC and AC characteristics of tunnel field-effect transistors (TFETs). Using the Sentaurus simulation tools, we show the impacts of trap density distribution and trap type on the n-type double gate- (DG-) TFET. The results show that the donor-type and acceptor-type ITs have the great influence on DC characteristic at midgap. Donor-like and acceptor-like ITs have different mechanism of the turn-on characteristics. The flat band shift changes obviously and differently in the AC analysis, which results in contrast of peak shift of Miller capacitorCgdfor n-type TFETs with donor-like and acceptor-like ITs.

Can Interface Traps Suppress TFET Ambipolarity?

The impact of semiconductor/oxide interface traps (ITs) on the turn-on characteristics of tunnel field-effect transistors (TFETs) is carefully investigated through TCAD. IT density is treated as a 2-D continuum. Both a conventional and an advanced nanowire TFET, designed to fulfill ITRS specs, are addressed. Surprisingly, in conventional TFETs, high concentrations of acceptor-like ITs can suppress device ambipolarity, thus reducing transistor's OFF-state current.

Insight into the output characteristics of III-V tunneling field effect transistors

The mechanism of the drain current saturation in the output characteristics of III-V tunneling field effect transistor (TFET) is explained in detail using numerical simulations as well as physics-based analytical models. We clearly identify the impact of the source doping on delayed output saturation, and non-linear turn on behavior observed in the output characteristics of TFET. Our model uses Wentzen-Krammel-Brillouin approximation and considers the exponentially decaying potential profile in the channel. The choice of source doping in III-V p-channel TFET requires tradeoff between maintaining steep switching and delayed saturation voltage which is of importance for complementary TFET logic.

Dependency of Tunneling Field-Effect Transistor(TFET) Characteristics on Operation Regions

In this paper, two competing mechanisms determining drain current of tunneling field-effect transistors (TFETs) have been investigated such as band-to-band tunneling and drift. Based on the results, the characteristics of TFETs have been discussed in the tunneling-dominant and driftdominant region.

Drain voltage dependent analytical model of tunnel field-effect transistors

Tunnel field-effect transistors (TFETs) are potential successors of metal-oxide-semiconductor FETs because they promise superior input characteristics. However, the output characteristics of TFETs are poorly understood, and sometimes a superlinear onset, undesirable for circuit design, is observed. We present the first analytical model to include the impact of the drain voltage on the TFET performance. The model is developed for both a pure line-tunneling TFET and a pure point-tunneling TFET. Good agreement is observed with device simulations, especially for line-tunneling TFETs. Our model highlights and explains the superlinear onset of the output characteristics, thereby enabling an improved analysis of experimental data. Increasing the source doping level and switching to a smaller bandgap material can remove the undesired onset. We confirm this finding with our experimental data.

Vertical Si-Nanowire &lt;formula formulatype="inline"&gt;&lt;tex Notation="TeX"&gt;$n$&lt;/tex&gt;&lt;/formula&gt;-Type Tunneling FETs With Low Subthreshold Swing (&lt;formula formulatype="inline"&gt;&lt;tex Notation="TeX"&gt;$\leq \hbox{50}\ \hbox{mV/decade}$&lt;/tex&gt; &lt;/formula&gt;) at Room Temperature

This letter presents a Si nanowire based tunneling field-effect transistor (TFET) using a CMOS-compatible vertical gate-all-around structure. By minimizing the thermal budget with low-temperature dopant-segregated silicidation for the source-side dopant activation, excellent TFET characteristics were obtained. We have demonstrated for the first time the lowest ever reported subthreshold swing (SS) of 30 mV/decade at room temperature. In addition, we reported a very convincing SS of 50 mV/decade for close to three decades of drain current. Moreover, our TFET device exhibits excellent characteristics without ambipolar behavior and with high I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> ratio (10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> ), as well as low Drain-Induced Barrier Lowering of 70 mV/V.