Effects of Pillar Conditions on DC/AC Characteristics of Tunnel Field-effect Transistor with Vertical Structures

Abstract

To investigate the effects of various pillar conditions such as pillar thickness (T<SUB>pillar</SUB>), pillar height (T<SUB>Si</SUB>), and doping concentration of pillar on DC characteristics of TFETs with vertical structures (TFET<SUB>VS</SUB>) and AC switching characteristics of TFET<SUB>VS</SUB> inverters, Mixed-mode device and circuit TCAD simulations are performed. As 1) the T<SUB>pillar</SUB> is thicker, 2) the T<SUB>Si</SUB> is increased, and 3) the doping concentration of the pillar is reduced, the tunneling current between source and channel gets increased and the gate-to-drain capacitance (C<SUB>GD</SUB>)-gate voltage (V<SUB>G</SUB>) curve becomes positive-shifted due to the weaker controllability of V<SUB>G</SUB> on the drain-side channel. Through the transient responses of TFET<SUB>VS</SUB> inverters with various pillar conditions, it is revealed that AC switching performance can be improved by the enhanced tunneling current and the positive-shifted C<SUB>GD</SUB>-V<SUB>G</SUB> curve caused by the weaker V<SUB>G</SUB> controllability on the drain-side channel.