Study of gate leakage current paths in p-channel tunnel field-effect transistor by current separation measurement and device simulation

Abstract

Scaling the gate dielectric is a key to improving the steep switching characteristics of tunnel field-effect transistors (TFETs). The effect of the gate leakage current caused by this scaling has not fully been investigated until now. In this work, gate leakage current paths in a p-channel TFET are experimentally investigated by designing three types of measurement setup for separating the current paths. Our measurements reveal that the so-called gate-edge leakage current that directly flows from the gate into the source adversely affects the subthreshold characteristics of the source current. We also report that the areal leakage current tunneling from the gate to the channel causes the OFF current to increase. A device simulation is performed to separate the contribution of electron gate tunneling from that of hole gate tunneling and to understand the mechanism underlying these tunnelings, which reveals that electron tunneling occurring in the nanometer-scale source–gate overlap determines the gate leakage. Structural engineering around the source–channel overlap plays an important role in achieving high-performance TFETs.