Characteristics Of Metal-oxide-semiconductor Field-effect Transistors Research Articles

A Voltage Equalization Strategy for Series-Connected SiC MOSFET Applications

A novel clamped voltage equalization strategy is presented for series-connected Silicon Carbide (SiC) Metal–Oxide semiconductor Field-Effect transistors (MOSFETs) in this paper. Differences in device parameters and circuit asymmetry result in the uneven voltage distribution of series-connected SiC MOSFETs, which threatens the safe operation of the circuit. Dynamic voltage equalization is difficult to achieve due to the fast switching speed of SiC MOSFETs. This paper analyzes the switching characteristics and dynamic voltage equalization characteristics of SiC MOSFETs. Based on the analysis, an energy recovery strategy based on the clamping auxiliary circuit is proposed. A 2.8 kW (50 KHz) prototype is fabricated and tested to verify the strategy. Measurement results show that the maximum voltage stress is suppressed from 600 V to less than 320 V in the experimental condition.

Research Progress on Metal-Oxide Semiconductor Field Effect Transistors

Metal-Oxide Semiconductor Field Effect Transistors (MOSFETs) have been constantly pursued in recent years as one of the indispensable components in modern electronic equipment, with better MOSFETs and a wider range of MOSFET applications. This study presents the classification and characteristics of MOSFETs briefly, investigates their applications in various aspects, and assesses the potential future development patterns of MOSFETs. This thesis research shows that different MOS tubes have different characteristics. MOSFETs mainly use enhanced N- and P-channel Metal-Oxide Semiconductor (NMOS and PMOS), complementary Metal-Oxide Semiconductor (CMOS), and neuronal Metal-Oxide Semiconductor (MOS). NMOS has the characteristics of less switching loss, a low threshold voltage, and is good for improving integration, but the temperature rises, etc. PMOS has the characteristics of being suitable for high-end drives and easy to drive and control, but the working speed is low and the switching loss is high. CMOS has the characteristics of good temperature stability, radiation resistance, and process complexity. Neuronal MOS can change the threshold voltage of the first input gate, and the floating gate charge can be preserved for a long time, so it is suitable for neural network applications. MOSFET can also be applied to switching and sensor applications. MOSFET applications generally belong to the fields of digital and analog circuits, communications, computers, etc. However, the application of MOS tubes in some fields still has defects. It is concluded that MOS tubes can be better used in other fields in the future, such as environmental monitoring and protection, chemical process control, etc. The future direction of MOS tubes includes higher performance, higher integration, fewer limitations, and so on. This thesis provides the direction for improvement of MOSFET research, which provides the basis and reference for subsequent research.

Dynamic Dead-Time Compensation Method Based on Switching Characteristics of the MOSFET for PMSM Drive System

In order to effectively avoid the shoot-through issue of the semiconductor device (such as the power metal-oxide-semiconductor field-effect transistor (MOSFET)) adopted in the phase leg of the motor drives, a dead-time zone should be inserted. However, the nonlinearity caused by the dead-time effect will bring about voltage/current distortion, as well as high-order harmonics, which largely degrades the performance of motor drives, especially in low-speed operations with slight loads. In this paper, a dead-time compensation method is proposed to suppress such side effects caused by dead-time zones and improve the performance of motor drives. Compared with other existing methods, the proposed method is mainly focused on the switching characteristics of the power MOSFET, which is directly relative to the compensation time in each pulse-width modulation (PWM) period. Firstly, a detailed derivation process is elaborated to reveal the relationship between compensation time and the switching performance of the MOSFET. Meanwhile, the switching process of the MOSFET is also well analyzed, which summarizes the variations in the switching time of the MOSFET with a varied load current. Then, the multipulse test (MPT) is carried out to obtain accurate values of the switching time with the varied load current in a wide range (0–80 A) and form a 2D lookup table. As a result, the compensation method can easily be realized by combining the lookup table and linear interpolation based on the phase current of the motor dynamically. Finally, the effectiveness of the proposed method is verified based on a 12 V permanent magnet synchronous machine (PMSM) drive system. According to the relative experiment results, it can be clearly observed that the time-domain waveform distortion, high-order harmonics, and total harmonic distortion (THD) value are reduced significantly with the proposed dynamic compensation method.

In vestigation the Impact of Silicon Film Thickness on FDSOI and PDSOI MOSFET Characteristics

The performance of chip is degraded because of the short-channel effect (SCE) as the metal oxide semiconductor field effect transistor (MOSFET) size scales down. Silicon on insulator (SOI) technology helps to reduce the short channel effects and permits a good solution to the miniaturization. The electrical characteristics of fully depleted SOI (FDSOI) and partially depleted SOI (PDSOI) n-channel MOSFET (N-MOSFET) are investigated as silicon film thickness is varied in this paper. Both transistors are compared in terms of electrical parameters which are the threshold voltage, subthreshold slope, on-state current, leakage current and drain induced barrier lowering (DIBL). Silvaco TCAD tools are used for simulating both PDSOI and FDSOI MOSFETs. FDSOI MOSFET is superior to PDSOI MOSFET based on found simulation results.

Impact of Nitridation on Bias Temperature Instability and Hard Breakdown Characteristics of SiON MOSFETs.

We study how nitridation, applied to SiON gate layers, impacts the reliability of planar metal-oxide-semiconductor field effect transistors (MOSFETs) subjected to negative and positive bias temperature instability (N/PBTI) as well as hard breakdown (HBD) characteristics of these devices. Experimental data demonstrate that p-channel transistors with SiON layers characterized by a higher nitrogen concentration have poorer NBTI reliability compared to their counterparts with a lower nitrogen content, while PBTI in n-channel devices is negligibly weak in all samples independently of the nitrogen concentration. The Weibull distribution of HBD fields extracted from experimental data in devices with a higher N density are shifted towards lower values with respect to that measured in MOSFETs, and SiON films have a lower nitrogen concentration. Based on these findings, we conclude that a higher nitrogen concentration results in the aggravation of BTI robustness and HBD characteristics.

An approach for extracting the SiC/SiO2 SiC MOSFET interface trap distribution and study during short circuit

The high trap density at the SiC/SiO2 interface is still the major reliability issue of silicon carbide (SiC) metal-oxide-semiconductor field effect transistors (MOSFETs). In this paper, we analyse the influence of the channel region and JFET region on the C-V curve from the band perspective. We proposed an approach to extract the oxide interface characteristics of a SiC MOSFET by fitting the measured C-V characteristic curve with the TCAD simulated curve. Then, the extracted SiC/SiO2 interface characteristics were verified by fitting the measured and simulated I-V curves and threshold voltages (VTH) at different lattice temperatures. Next, the extracted interface characteristics and the fixed interface charge were separately added to the TCAD model for comparison of the short-circuit simulations. It was found that the former model failed earlier than the latter and that the peak short-circuit current value was lower. The causes of these two phenomena are attributed to the different leakage degrees of the hole current in the Pbase region below the channel caused by interface traps and the difference in the channel mobility, respectively. Last, according to current shunt theory, P-type blocks were added below the JFET area to reduce the current during a short-circuit transient, thus improving the capacity to withstand a short circuit by approximately 22.4%.

MOSFET modeling of [formula omitted] CMOS technology at 4.2K using BP neural network

Cryogenic CMOS circuits are widely applied to various fields, such as infrared focal plane arrays, space exploration, and quantum computing. The carrier freeze-out effect at cryogenic temperatures leads to abnormal changes in the characterization of the devices. These cause the performance degradation of circuits or even failure to work. As the industry-standard models provided by manufacturers of CMOS technology cannot describe the cryogenic effects, a complete and precise cryogenic model is required for circuit simulation at cryogenic temperatures. This paper presents the characterization of Semiconductor Manufacturing International Corporation (SMIC) 0.18μm CMOS technology at the liquid helium temperature (LHT). To solve the above problem, a metal–oxide–semiconductor field-effect transistor (MOSFET) modeling method at cryogenic temperatures using a back propagation (BP) neural network is proposed. The cryogenic model is first revised based on the BSIM model by extracting physical parameters. Then an optimization model predicted by BP neural network is proposed to calibrate the cryogenic effects. The cryo-model composed of the revised BSIM model and the optimization model can accurately describe the characteristics of MOSFETs with various aspect ratios under different bias voltages at 4.2K, which is not accessible for the standard BSIM model. Meanwhile, the optimization model based on BP neural network has been translated into Verilog-A language to be applied to the SPICE simulator successfully.

A core drain current model for β-Ga2O3 power MOSFETs based on surface potential

For the first time, a core drain current model based on surface potential without any implicit functions is developed for beta-phase gallium oxide (β-Ga2O3) power metal-oxide-semiconductor field-effect transistors (MOSFETs). The surface potential solution is analytically deduced by solving the Poisson equation with appropriate simplification assumptions in accumulation, partial-depletion, and full-depletion modes. Then, the drain current expression is analytically derived from the Pao–Sah integral as a function of the mobile charge density obtained from the surface potential at the source and drain terminals. In addition, nonlinear resistors in the source/drain access region are considered. It continuously predicts the characteristics of β-Ga2O3 power MOSFETs in all operation modes, including accumulation mode, partial-depletion mode, and full-depletion mode. Furthermore, the validity of the model is verified by comparing the results of the model with the numerical simulations carried out with the technology computer-aided design (TCAD) tool ATLAS Device Simulator from Silvaco. Good agreement between the proposed model and TCAD simulations is shown for β-Ga2O3 power MOSFETs with different intrinsic channel lengths, channel doping concentrations, and channel thicknesses. Ultimately, the Gummel symmetry test and the harmonic balance simulation test are performed to validate the model’s robustness and convergence.

An analytical switching model of SiC MOSFET considering the junction temperature characteristics

In order to provide convenience in the design work as the manufacturer-supplied models of silicon carbide (SiC) metal oxide semiconductor field effect transistor (MOSFET) are generally only applicable to specific software, an analytical switching model of SiC MOSFET considering the junction temperature characteristics based on MATLAB is proposed in this article. The junction temperature characteristics of the parameters required for the switching process, including threshold voltage, on-resistance and transfer characteristics of SiC MOSFET, threshold voltage and output characteristics of body diode, which are extracted from the datasheet of the SiC MOSFET provided by the manufacturer. Then a model for the transient process of the test circuit, including the non-linear capacitance, the parasitic resistance and parasitic inductance from package and the printed circuit board is created. After that, each sub-stage of the switching process is analyzed in detail, then the analytical model is solved numerically using MATLAB. Finally, the SiC MOSFET C3M0075120K manufactured by Wolfspeed is selected as the case study to verify the built model, and the accuracy is validated by comparing with the LTspice simulation and experiment results. As a result, the proposed model can be applied, especially in designs involving junction temperatures.

Electrical Characteristics of Diamond MOSFET with 2DHG on a Heteroepitaxial Diamond Substrate

In this work, hydrogen-terminated diamond (H-diamond) metal-oxide-semiconductor field-effect-transistors (MOSFETs) on a heteroepitaxial diamond substrate with an Al2O3 dielectric and a passivation layer were characterized. The full-width at half maximum value of the diamond (004) X-ray rocking curve was 205.9 arcsec. The maximum output current density and transconductance of the MOSFET were 172 mA/mm and 10.4 mS/mm, respectively. The effect of a low-temperature annealing process on electrical properties was also investigated. After the annealing process in N2 atmosphere, the threshold voltage (Vth) and flat-band voltage (VFB) shifts to negative direction due to loss of negative charges. After annealing at 423 K for 3 min, the maximum value of hole field effective mobility (μeff) increases by 27% at Vth − VGS = 2 V. The results, which are not inferior to those based on homoepitaxial diamond, promote the application of heteroepitaxial diamond in the field of electronic devices.

A fractional-order equivalent model for characterizing the interelectrode capacitance of MOSFETs

PurposeThis paper aims to characterize the relationship between the interelectrode capacitance (C) of metal-oxide-semiconductor field-effect transistors (MOSFETs) and the applied bias voltage (V) by a fractional-order equivalent model.Design/methodology/approachA Riemann–Liouville-type fractional-order equivalent model is proposed for the C–V characteristic of MOSFETs, which is based on the mathematical relationship between fractional calculus and the semiconductor physical model for the interelectrode capacitance of metal oxide semiconductor structure. The C–V characteristic data of an N-channel MOSFET are obtained by Silvaco TCAD simulation. A differential evolution-based offline scheme is exploited for the parameter identification of the proposed model.FindingsAccording to the results of theoretical analysis, mathematical derivation, simulation and comparison, this paper illustrates that, along with the variation of bias voltage applied, the interelectrode capacitance (C) of MOSFETs performs a fractional-order characteristic.Originality/valueThis work uncovers the fractional-order characteristic of MOSFETs’ interelectrode capacitance. By the proposed model, the influence of doping concentration on the gate leakage parasitic capacitance of MOSFETs can be revealed. In the pre-defined doping concentration range, the relative error of the proposed model is less than 5% for the description of C–V characteristics of metal-oxide-semiconductor field-effect transistors (MOSFETs). Compared to some existing models, the proposed model has advantages in both model accuracy and model complexity, and the variation of model parameters can directly reflect the relationship between the characteristics of MOSFETs and the doping concentration of materials. Accordingly, the proposed model can be used for the microcosmic mechanism analysis of MOSFETs. The results of the analysis produce evidence for the widespread existence of fractional-order characteristics in the physical world.

Nucleation sites of expanded stacking faults detected by in operando x-ray topography analysis to design epitaxial layers for bipolar-degradation-free SiC MOSFETs

We investigated the nucleation sites of expanded single Shockley-type stacking faults (1SSFs) in a silicon carbide (SiC) metal–oxide–semiconductor field effect transistor (MOSFET) and demonstrated epitaxial layers designed for bipolar-degradation-free SiC MOSFETs. Since the sufficient hole density just below the basal plane dislocation (BPD)-threading edge dislocation (TED) conversion points induces 1SSF expansion, we derived the dependence of the nucleation depth on the applied current condition from the BPD-TED conversion points of 1SSFs. We first simulated and determined the three-step current conditions applied to a body diode in a SiC MOSFET so that a sufficient amount of holes would be supplied to the drift layer, to the buffer layer, and inside the substrate in the SiC MOSFET. An in operando x-ray topography analysis was conducted with the determined conditions for dynamically visualizing 1SSF expansion motions, and 1SSFs expanded at different forward current densities were successfully extracted. The depths of the BPD-TED conversion points of the extracted 1SSFs were analyzed, and it was experimentally clarified that these depths, i.e., the nucleation sites of expanded 1SSFs, became deeper with forward current densities. The bipolar degradation characteristics of SiC MOSFETs were evaluated as a function of the forward current density, and the validity of the simulation model was verified by experimental results. We also confirmed that bipolar degradation can be suppressed to some extent by using a substrate with a low BPD density, and SiC MOSFETs with a high-nitrogen-concentration epitaxial layer showed high reliability under bipolar operation. Depending on the application of SiC MOSFETs, the epitaxial layers should be designed to prevent the hole density inside the substrate from exceeding the threshold for 1SSF expansion.

Modeling electrostatic potential in FDSOI MOSFETS: An approach based on homotopy perturbations

Abstract Modeling of the electrostatic potential for fully depleted (FD) silicon-on-insulator (SOI) metal-oxide-semiconductor field effect transistor (MOSFET) is presented in this article. The modeling is based on the analytical solution of two-dimensional Poisson’s equation obtained by using the homotopy perturbation method (HPM). The HPM with suitable boundary conditions results in the so-called HPM solution in general and closed-form, independent of the surface potential. The HPM solution has been applied in modeling the output characteristics of the FDSOI MOSFET, which show good agreement compared with the numerical results.

Development of solderable layer on power MOSFET for double-side bonding

The use of power metal oxide semiconductor field effect transistor (MOSFET) packages is being actively explored to improve heat dissipation by fast switching. The double-side cooling package structure of power MOSFETs is considered efficient for heat dissipation, which requires bonding the MOSFET with Cu lead frames on both the top and bottom sides by soldering. Although soldering can typically be performed for the bottom side, it is challenging to perform on the top side due to Al metallization and has, therefore, been rarely reported. In this study, we developed various layers on the top side of a MOSFET to enable soldering between the MOSFET and Cu lead frame to realize a double-side cooling package. After depositing the thin films on the top side of the MOSFET with Ag and Ni materials, we fabricated the double-side package in the form of a TO-263 package to evaluate the electrical characteristics of the power MOSFET. In addition, we fabricated a typical TO-263 package having only the bottom-side cooling structure and compared its performance with that of the double-side cooling structure. Thermal cycle tests were performed up to 1500 cycles for 25 min at each extreme temperature in the −55 to 125 °C range. Electron backscatter diffraction was conducted on Al metallization beneath the solderable layers to analyze the change in the grain orientation and size of the Al layer. In addition, the stress behavior of the Al layer according to the presence of the Ni layer was compared using FEM simulation. Our findings provide the optimal solderable metallization of 600-nm-thick Ni and Ag layers each for bonding on the top layer of a power MOSFET, realizing a double-side cooling package for power MOSFETs.

Fabrication of inversion p-channel MOSFET with a nitrogen-doped diamond body

A normally-off inversion p-channel metal-oxide-semiconductor field-effect transistor (MOSFET) with a nitrogen (N)-doped diamond body deposited using microwave plasma-enhanced chemical vapor deposition (MPECVD) was fabricated. The MOSFET exhibited a drain current density of −1.7 mA/mm. Thus far, this value is similar to the device performance of the inversion p-channel MOSFET fabricated using a phosphorus (P)-doped n-type diamond body. The N2 used for N-doping is safer than the PH3 used for P-doping; moreover, the doping concentration is highly controllable. Because the MOSFET, which is a classical electronic device, is driven by a gate voltage, smooth functioning was possible even at a deep donor level. The observed characteristics of the classic MOSFET operating via an N-doped body are crucial for the development of diamond power devices. In this paper, we discuss the significance of the N-doped diamond body and electrical characteristics of the inversion p-channel MOSFET fabricated using an N-doped diamond body.

Developed non-destructive verification methods for accelerated temperature cycling of power MOSFETs

This study deals with the non-destructive test methods applied in the industry for SiC power metal-oxide-semiconductor field-effect transistors (MOSFETs). Scanning acoustic tomography (SAT) is used for testing SiC power MOSFETs, which are widely used in high-power electronic devices and electric vehicles. In this paper, we propose an automatic calculation method through SAT image conversion. Based on the automatically calculated delamination area, the device failure was determined, and the exact failure mechanism was identified. Existing verification methods require a lot of skills. In addition to measuring the electrical characteristics of SiC MOSFETs, internal structure analysis using X-ray and pass/fail judgment through SAM were performed. However, the auto-counting program SAT method reduces unnecessary verification methods and simultaneously detects the process of degradation of the SiC MOSFETs and the cause of internal failure. An SAT image first goes through a program that optimizes image recognition by adjusting the contrast and threshold. These preparation steps play an important role in accurately recognizing the delamination area. These steps and the verification method proposed to evaluate the reliability of SiC power MOSFETs are detailed in this article. The degradation process of the device is presented and discussed by applying an accelerated temperature cycling test and high voltage at the device's gate terminal.

Improving the Performance of the ToGoFET Probe: Advances in Design, Fabrication, and Signal Processing.

We report recent improvements of the tip-on-gate of field-effect-transistor (ToGoFET) probe used for capacitive measurement. Probe structure, fabrication, and signal processing were modified. The inbuilt metal-oxide-semiconductor field-effect-transistor (MOSFET) was redesigned to ensure reliable probe operation. Fabrication was based on the standard complementary metal-oxide-semiconductor (CMOS) process, and trench formation and the channel definition were modified. Demodulation of the amplitude-modulated drain current was varied, enhancing the signal-to-noise ratio. The I-V characteristics of the inbuilt MOSFET reflect the design and fabrication modifications, and measurement of a buried electrode revealed improved ToGoFET imaging performance. The minimum measurable value was enhanced 20-fold.

An Improved Modulation Method for Suppressing High Frequency Common-Mode Voltage in SiC Motor Drive System

High-frequency common-mode voltage generated by inverters causes severe negative effects, particularly in silicon carbide (SiC) Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs)-driven motors. Additionally, common suppression strategies would increase hardware expenses or sacrifice the switching speed of SiC devices. This article proposes an improved no-zero vector modulation strategy to suppress high-frequency common-mode voltage without increasing the cost of hardware. In this method, only nonzero vectors are utilized to reduce common-mode voltage. Firstly, the influence of different switching states on the characteristics of SiC MOSFETs has been studied by double-pulse tests, which explains why zero vectors will cause more serious voltage oscillations. Secondly, common-mode voltage suppression failure caused by the high-frequency dead zone effect has been analyzed in detail. Based on traditional Active Zero State Pulse Width Modulation (AZSPWM), complementary device conduction logic and dead-zone compensation methods are proposed. In switching moments, different turn-on logic is selected to ensure that only one switch acts, and different dead zone compensation methods are selected to deal with the common-mode suppression failure, which effectively avoids high-frequency common-mode voltage spikes. Finally, simulation and experimental results verify that the improved modulation algorithm can effectively suppress high-frequency common-mode voltage.

Effect of high- and low-side blocking on short-circuit characteristics of SiC MOSFET

Silicon carbide (SiC) metal oxide semiconductor field-effect transistors (MOSFETs) are susceptible to unexpected short-circuit (SC) impacts in high-voltage inverters operating in complex applications. This paper presents a research on the effect of high-side blocking and classical low-side blocking on short circuit characteristics. Simulation of the steady-state electric field, which equivalent to the states after LSB and HSB, was performed. The obvious electric field concentration appears in the source-drain pn junction of the DUT after the LSB, and is much larger in value than that appearing in the DUT after the HSB. DUTs, which failed, were decapsulated from the side of the drain to allow for an emission microscope (EMMI) investigation. In response to the results of the EMMI investigation, it was discussed that the occurrence of source leakage was caused by electric field concentration after the DUT is blocked. The hazards of this failure and the expected further research are mentioned simply.

The reverse recovery characteristics of an SiC superjunction MOSFET with a p-type Schottky diode embedded at the drain side for improved reliability

The improvement achieved in the reverse recovery characteristics of an SiC superjunction metal–oxide–semiconductor field-effect transistor (MOSFET) by embedding a p-type Schottky contact at the drain terminal and removing the $${N}^{++}$$ substrate is presented. The carrier injection into the drain terminal during the reverse recovery phase is drastically reduced in the proposed device due to the Schottky barrier, thereby eliminating the need for an external free-wheeling diode. The calibrated two-dimensional (2D) numerical simulations using Synopsys technology computer-aided design (TCAD) software reveal an improvement in (i) the reverse recovery charge by 70%, (ii) the switching loss due to reverse recovery by 70%, and (iii) Baliga’s figure of merit (FOM) by 4.5% compared with the device without the Schottky contact. Furthermore, the variation in the device and circuit characteristics is analyzed from 300 to 500 K using nonisothermal simulations.