Channel Metal Oxide Semiconductor Field Research Articles

Process Development of Dislocation-Free SiGe P-Channel in FinFET Technology

SiGe channel metal oxide semiconductor field effect transistor (MOSFET) became a choice of material as a performance booster in leading edge logic technologies. In this study, we demonstrate integration solutions for dual fin formation (Si for nFET, SiGe for pFET) using buried SiGe channel approach on 300 mm Si wafer. Plasma-induced damage (PID) layer, which thickness ranges from 0.5 nm to 2.5 nm, was observed after Si trench (p-trench) etch for SiGe EPI growth. This PID inorganic layer leads to SiGe dislocation defect. And careful sequencing and optimization of oxidation and wet removal steps were able to realize defect-free SiGe EPI channel along with a thin buffer SiGe layer. Besides, margin assessment of p-trench based buried SiGe approach was also presented in this study. Moreover, dual fin etch was demonstrated via inductively coupled plasma (ICP) using ALD-like function. The depth loading between SiGe and Si Fin was tunable via varying repeated cycles of advanced pulsing step, and less than 40 A of depth loading can be achieved. The progress reported represents a major leap for SiGe channel integration and paves the way for massive production.

Process Development of Dislocation-Free SiGe P-Channel in FinFET Technology

SiGe channel metal oxide semiconductor field effect transistor (MOSFET) became a choice of material as a performance booster in leading edge logic technologies. In this study, we demonstrate integration solutions for dual Fin formation (Si for nFET, SiGe for pFET) using buried SiGe channel approach on 300 mm Si wafer. Plasma-induced damage (PID) layer, which thickness ranges from 0.5 nm to 2.5 nm, was observed after Si trench (p-trench) etch for SiGe EPI growth. This PID inorganic layer leads to SiGe dislocation defect. And careful sequencing and optimization of oxidation and wet removal steps were able to realize defect-free SiGe EPI channel along with a thin buffer SiGe layer. Besides, margin assessment of p-trench based buried SiGe approach was also presented in this study. Moreover, dual Fin etch was demonstrated via inductively coupled plasma (ICP) using ALD-like function. The depth loading between SiGe and Si Fin was tunable via varying repeated cycles of advanced pulsing step, and less than 40 A of depth loading can be achieved. The progress reported represents a major leap for SiGe channel integration and paves the way for massive production.

Reduction of Source/Drain Series Resistance in Fin Channel MOSFETs Using Selective Oxidation Technique

A novel selective oxidation process has been developed for low source/drain (S/D) series resistance of the fin channel metal oxide semiconductor field effect transistor (MOSFET). Using this technique, the selective oxidation fin-channel MOSFET (SoxFET) has the gate-all-around structure and gradually enhanced S/D extension regions. The SoxFET demonstrated over 70% reduction in S/D series resistance compared to the control device. Moreover, it was found that the SoxFET behaved better in performance, not only a higher drive current but also higher transconductances with suppressing subthreshold swing and drain induced barrier lowering (DIBL) characteristics, than the control device. The saturation current, threshold voltage, peak linear transconductance, peak saturation transconductance, subthreshold swing, and DIBL for the fabricated SoxFET are 305 μA/μm, 0.33 V, 13.5 μS, 76.4 μS, 78 mV/dec, and 62 mV/V, respectively.

Effects of Total Dose Radiation on Single Event Effect of the Uniaxial Strained Si Nano NMOSFET

The effect of total dose radiation on the single event effect of uniaxial strained Si Nano channel metal oxide semiconductor field effect transistor (NMOSFET) was studied by TCAD simulation. By comparing the experimental results, the TCAD simulation model of the 50 nm strained Si NMOS device is established. The model is used to simulate the off-state single event effect (V ds = 0.05) of NMOSFET under the total dose radiation. The results show that total dose radiation increases the body potential of NMOSFET devices and intensifies the single event transient process of NMOSFET devices. The transient current increases by 4.88% and the drain charge increases by 29.15% under the total dose of 2KGy, which indicates that the effect of total dose radiation on the single event effect is the main factor affecting the collection of drain charge. Therefore, the experimental results and the established model provide good reference for the study of irradiation reliability of the uniaxial strained Si Nano NMOSFET and the application of strained integrated circuits.

Influence of Structural Parameters on the Behavior of an Asymmetric Linearly Graded Workfunction Trapezoidal Gate SOI MOSFET

This paper presents a dual metal trapezoidal recessed channel metal oxide semiconductor field effect transistor (MOSFET) embedded with asymmetric stack gate with linearly graded metal work-function technique to improve the carrier transport efficiency and device switching performance. The analytical model for the proposed asymmetric-linearly graded trapezoidal gate (ASY–LGTG) silicon on insulator (SOI) MOSFET has been developed considering parabolic approximation of 2-D Poisson’s equation. The threshold voltage of the device is extracted using minimum surface potential. The simulation work has been carried out using a Silvaco TCAD tool to validate the results of the analytical model. This grooved structure exhibits the corner effect, which plays a dynamic role in the improvement of the device performance. However, the impact of the corner effect can be controlled by the groove corner angle and doping concentration. We have also investigated the impact of different structural parameters such as negative junction depth (NJD), corner angle, substrate doping and stack gate features (upper oxide permittivity and oxide thickness ratio) on the performance of minimum surface potential, sub-threshold slope (SS), drain induced barrier lowering (DIBL), threshold voltage and device switching characteristics.

A New Surface Potential and Drain Current Model of Dual Material Gate Short Channel Metal Oxide Semiconductor Field Effect Transistor in Sub-Threshold Regime: Application to High-k Material HfO2

A New Surface Potential and Drain Current Model of Dual Material Gate Short Channel Metal Oxide Semiconductor Field Effect Transistor in Sub-Threshold Regime: Application to High-k Material HfO₂

Total Dose Radiation Response of Capacitance Characteristic for Nano-scale NMOS

The carrier transport in uniaxial strained Si N channel metal oxide semiconductor field effect transistor (NMOSFET) irradiated by gamma rays is analysed. Based on the total dose irradiation effect, an analytical model for differential capacitance of uniaxial strained Si Nano NMOSFET is established. Based on this model, numerical calculation is carried out by MATLAB. The influence of geometric parameters and total dose on differential capacitance is simulated. Meanwhile, the simulation results match the calculation results very well, which validate the accuracy of the model. Therefore, the model provides a good reference for the irradiation reliability of uniaxial strained Si nano NMOSFET and the application of strained integrated circuits.

Drain Current Modulation of a Single Drain MOSFET by Lorentz Force for Magnetic Sensing Application.

This paper reports a detailed analysis of the drain current modulation of a single-drain normal-gate n channel metal-oxide semiconductor field effect transistor (n-MOSFET) under an on-chip magnetic field. A single-drain n-MOSFET has been fabricated and placed in the center of a square-shaped metal loop which generates the on-chip magnetic field. The proposed device designed is much smaller in size with respect to the metal loop, which ensures that the generated magnetic field is approximately uniform. The change of drain current and change of bulk current per micron device width has been measured. The result shows that the difference drain current is about 145 µA for the maximum applied magnetic field. Such changes occur from the applied Lorentz force to push out the carriers from the channel. Based on the drain current difference, the change in effective mobility has been detected up to 4.227%. Furthermore, a detailed investigation reveals that the device behavior is quite different in subthreshold and saturation region. A change of 50.24 µA bulk current has also been measured. Finally, the device has been verified for use as a magnetic sensor with sensitivity 4.084% (29.6 T−1), which is very effective as compared to other previously reported works for a single device.

Study on high mobility In0.6Ga0.4As channel MOSHEMT and MOSFET

High-mobility In0.6Ga0.4As channel metal oxide semiconductor high electron mobility transistor (MOSHEMT) and metal oxide semiconductor field effect transistor (MOSFET) are investigated based on simulation and experiment in this paper. It is found that InAlAs barrier layer has a great influence on the characteristics of In0.6Ga0.4As MOSHEMT. In0.6Ga0.4As MOSHEMT exhibits excellent electrical characteristics compared with In0.6Ga0.4As MOSFET. The experimental results show that the effective channel mobility of MOSHEMT is 2812 cm2/V·s-1, which is 3.2 times that of MOSFET. A 0.02 mm gate length MOSHEMT shows higher drive current, peak transconductance, Ion/Ioff ratio and gate breakdown voltage and lower sub-threshold swing than the MOSFET with the same gate length.

Analytical modeling of quantum threshold voltage for triple gate MOSFET

In this work, a physically based analytical quantum threshold voltage model for the triple gate long channel metal oxide semiconductor field effect transistor is developed. The proposed model is based on the analytical solution of two-dimensional Poisson and two-dimensional Schrödinger equation. Proposed model is extended for short channel devices by including semi-empirical correction. The impact of effective mass variation with film thicknesses is also discussed using the proposed model. All models are fully validated against the professional numerical device simulator for a wide range of device geometries.

Si–Ge interdiffusion under oxidizing conditions in epitaxial SiGe heterostructures with high compressive stress

Si–Ge interdiffusion under oxidizing and inert conditions has been studied in epitaxial relaxed Si1−xGex/compressive Si1−yGey/relaxed Si1−xGex heterostructures. The interdiffusion was measured by secondary ion mass spectroscopy (SIMS) and studied using simulations. Within the SIMS accuracy, the measured Ge profiles show that oxidation has a small effect, if any, on the Si–Ge interdiffusion of these structures. These results suggest that oxidation does not accelerate Si–Ge interdiffusion significantly, which lessens process integration constraints for SiGe devices such as high mobility dual channel metal oxide semiconductor field effect transistors and heterostructure tunneling field effect transistors.

Residual order in the thermal oxide of a fully strained SiGe alloy on Si

Introduction Oxidation of SiGe alloy has been a target of research for both fundamental and technological reasons, as in the case of Si oxidation. It has been expected as the fabrication process for the gate oxide of SiGe channel metal oxide semiconductor field effect transistors (MOSFETs), which allows higher carrier mobility than that of Si channel MOSFETs [1]. In recent years, it has also been employed in the fabrication of SiGe-oninsulator and Ge-on-insulator substrates [2]. These substrates are employed to realize high-speed MOSFETs with channel materials of strained Si, SiGe, and Ge. However, the oxidation mechanism of SiGe alloy is still open to question, due to the complexity caused by lattice strain and diffusion of Ge atoms. The most characteristic phenomenon of SiGe oxidation is that Ge atoms are ejected from the interface between the surface oxide and the SiGe layer without the incorporation of Ge atoms into the oxide layer. Ge atoms accumulate at the SiO2/SiGe interface and diffuse into the SiGe layer [1,2]. In the case of a strained SiGe layer epitaxially grown on a Si substrate, the effects of strain relaxation and defect generation during the oxidation process must be taken into account. It is important to investigate the atomic structure of the thermally oxidized layer, because it allows us to understand what really happens at the oxidized interface. In the case of the thermally oxidized layer of Si, the Si atoms in the oxide layer still maintain order, which originates from the diamond structure of the parent Si crystal, although the structure appears to be amorphous at a glance. This provides an actual picture of the oxidation process and explains the almost perfect properties obtained by electric measurements of the SiO2/Si interface. In this study, the residual order in the thermal oxide layer on a fully strained SiGe alloy was investigated.

Study of strained-silicon channel metal–oxide–semiconductor field effect transistors by large angle convergent-beam electron diffraction

Strained-silicon p-type metal–oxide–semiconductor field effect transistors (pMOSFETs) have been investigated by large angle convergent-beam electron diffraction (LACBED). Longitudinal compressive strain is induced into the channel region of a p-type strained-silicon channel metal–oxide–semiconductor field effect transistor by a low-cost Ge pre-amorphization implantation for source/drain extension flow. Anomalously large longitudinal compressive strain, up to 2.5×10 −2, in the nanometer scale channel region of pMOSFETs has been measured using LACBED. We propose a novel scaling effect for the giant strain enhancement. Our experimental results and model analysis together reveal that the channel strain is inversely proportional to the shrinking channel length.

Ultra-Thin Si1−x Ge x Dislocation Blocking Layers for Ge/Strained Si CMOS Devices

We demonstrate ultra-thin (<150 nm) Si1−x Ge x dislocation blocking layers on Si substrates used for the fabrication of tensile-strained Si N channel metal oxide semiconductor (NMOS) and Ge P channel metal oxide semiconductor (PMOS) devices. These layers were grown using ultra high vacuum chemical vapor deposition (UHVCVD). The Ge mole fraction was varied in rapid, but distinct steps during the epitaxial layer growth. This results in several Si1−x Ge x interfaces in the epitaxially grown material with significant strain fields at these interfaces. The strain fields enable a dislocation blocking mechanism at the Si1−x Ge x interfaces on which we were able to deposit very smooth, atomically flat, tensile-strained Si and relaxed Ge layers for the fabrication of high mobility N and P channel metal oxide semiconductor (MOS) devices, respectively. Both N and P channel metal oxide semiconductor field effect transister (MOSFETs) were successfully fabricated using high-k dielectric and metal gates on these layers, demonstrating that this technique of using ultra-thin dislocation blocking layers might be ideal for incorporating high mobility channel materials in a conventional CMOS process.

Advanced Input/Output Technology Using Laterally Modulated Channel Metal–Oxide–Semiconductor Field Effect Transistor for 65-nm Node System on a Chip

Advanced input/output (I/O) technology is reported for leading-edge system on a chip (SoC) applications, including high-speed I/O and RF circuits. Our device having a laterally modulated channel shows sufficient reliability even at 3.3 V operation with the same size as a conventional 2.5 V device. Since this technology also improves current drivability, the layout area of an I/O circuit block can be reduced down to 55% because of a reduced total gate width. Moreover, a metal-on-gate (MOG) option has been developed for RF applications, and an fmax of 55 GHz was achieved.

Modeling negative bias temperature instabilities in hole channel metal–oxide–semiconductor field effect transistors with ultrathin gate oxide layers

The decrease of the threshold voltage Vth of hole channel metal–oxide–semiconductor field effect transistors with ultrathin gate dielectric layers under negative bias temperature stress is studied. A degradation model is developed that accounts for the generation of Si3≡Si• (Pb0) centers and bulk oxide defects, induced by the tunneling of electrons or holes through the gate dielectric layer during electrical stress. The model predicts that Vth shifts are mainly due to the tunneling of holes at low gate bias |VG|, typically below 1.5 V, while electrons are mainly responsible for these shifts at higher |VG|. Consequently, device lifetime at operating voltage, based on Vth shifts, should not be extrapolated from measurements performed at high gate bias. The impact of nitrogen incorporated at the Si/dielectric interface on Vth shifts is investigated next. The acceleration of device degradation when the amount of nitrogen increases is attributed to the increase in local interfacial strain, induced by the increase in bonding constraints, as well as to the increase in the density of Si–N–Si strained bonds that act as trapping centers of hydrogen species released during the electrical stress.

Origin of microwave noise from an n-channel metal–oxide–semiconductor field effect transistor

The physics of noise is a complex subject. It is often difficult to clearly identify the physical origin of the observed noise. Electronic noise at microwave frequencies is technologically very important and has been extensively studied. While it is well known that many physical phenomena give rise to output current fluctuations (i.e., noise) in a metal–oxide–semiconductor field effect transistor (MOSFET), few physical phenomena have a time constant that can contribute in the microwave range. Current physical models of MOSFET microwave noise are all based on thermal agitation of electrons (thermal noise). However, what is the correct temperature (lattice or electron) to use in the noise calculation is an ongoing debate in the literature. All the modeling efforts have been using noise measured from pristine devices as a test for validity. In this work, we studied the n-MOSFET microwave noise as a function of electrical stress induced degradation. Our experiments thus introduced a new dimension in the noise behavior study. The results of our experiments cannot be explained by any of the current existing models. All existing models discounted flicker noise as being too small at microwave frequency. Our experimental results compel us to reexamine the validity of this common assumption. While we are not quite able to prove conclusively, our evidences are clearly leaning toward defect-induced fluctuation (flicker noise) as the origin of microwave noise in a n-MOSFET

An asymmetric channel SOI nMOSFET for improving DC and microwave characteristics

Asymmetric doped channel metal oxide semiconductor field effect transistors (MOSFETs) have recently been investigated by several authors in bulk and silicon-on-insulator (SOI) technologies as a possible solution for the problems of premature drain breakdown, hot carrier effects, and threshold voltage rolloff issues in deep sub-micrometer devices. In this paper, the DC and microwave characteristics of the asymmetric doped channel fully depleted (FD) SOI MOSFET are presented and compared to conventional uniformly doped FD SOI MOSFET.

Observation of double peak in the substrate current versus gate voltage characteristics of n-channel metal–oxide–semiconductor field effect transistors

By employing sensitive current measurements at low drain voltages for n-channel metal–oxide–semiconductor field effect transistors with different channel dopings, substrate current versus gate voltage characteristics with two peaks were obtained for devices with low channel doping at 77 K. This differs from the single peak bell shaped curves reported in the literature. The data are analyzed and suggest that the second peak is due to the contribution of electron–electron interactions to the high energy tail of the electron energy distribution. Indirect contributions by the thermal tail of the electron energy distribution and ionized impurity scattering that make the second peak visible are also discussed.

Excellent Electrical Characteristics of Ultrafine Trench Isolation

An ultrafine trench isolation, by which a narrow channel metal oxide semiconductor field effect transistor (MOSFET) can be isolated with excellent electrical properties, was formed using a new fabrication process. A void‐free shape was realized by two‐step filling, and the trench edge shapes were drastically improved by oxide spacer formation. Down to the ultranarrow field space of 0.13 μm, the isolation breakdown voltage and the parasitic MOSFETs threshold voltage were maintained as high as 7.7 V and more than 6 V. The reduction in the effective channel width for the MOSFET, furthermore, was estimated to be as small as 0.05 μm, while it was shown that kink‐free MOSFET subthreshold characteristics were kept even without a sidewall implantation to suppress the concentration of the electric field at the channel edges.