Process Development of Dislocation-Free SiGe P-Channel in FinFET Technology

Abstract

SiGe channel metal oxide semiconductor field effect transistor (MOSFET) became a choice of material as a performance booster in leading edge logic technologies. In this study, we demonstrate integration solutions for dual fin formation (Si for nFET, SiGe for pFET) using buried SiGe channel approach on 300 mm Si wafer. Plasma-induced damage (PID) layer, which thickness ranges from 0.5 nm to 2.5 nm, was observed after Si trench (p-trench) etch for SiGe EPI growth. This PID inorganic layer leads to SiGe dislocation defect. And careful sequencing and optimization of oxidation and wet removal steps were able to realize defect-free SiGe EPI channel along with a thin buffer SiGe layer. Besides, margin assessment of p-trench based buried SiGe approach was also presented in this study. Moreover, dual fin etch was demonstrated via inductively coupled plasma (ICP) using ALD-like function. The depth loading between SiGe and Si Fin was tunable via varying repeated cycles of advanced pulsing step, and less than 40 A of depth loading can be achieved. The progress reported represents a major leap for SiGe channel integration and paves the way for massive production.