Channel Charge-coupled Device Research Articles

C2D8: An eight channel CCD readout electronics dedicated to low energy neutron detection

Position-sensitive detectors for cold and ultra-cold neutrons (UCN) are in use in fundamental research. In particular, measuring the properties of the quantum states of bouncing neutrons requires micro-metric spatial resolution. To this end, a Charge Coupled Device (CCD) coated with a thin conversion layer that allows a real time detection of neutron hits is under development at LPSC. In this paper, we present the design and performance of a dedicated electronic board designed to read-out eight CCDs simultaneously and operating under vacuum.

Design and optimization of BCCD in CMOS technology

This paper optimizes the buried channel charge-coupled device (BCCD) structure fabricated by complementary metal oxide semiconductor (CMOS) technology. The optimized BCCD has advantages of low noise, high integration and high image quality. The charge transfer process shows that interface traps, weak fringing fields and potential well between adjacent gates all cause the decrease of charge transfer efficiency (CTE). CTE and well capacity are simulated with different operating voltages and gap sizes. CTE can achieve 99.999% and the well capacity reaches up to 25 000 electrons for the gap size of 130 nm and the maximum operating voltage of 3 V.

Analysis and simulation of entirely saturated unilateral laser spot tails in BCCD.

A new phenomenon involving the entire saturation of unilateral tails of buried channel charge-coupled devices (BCCDs) under laser radiation is observed in this study. A physical model related to this phenomenon is constructed based on the assumption that the charge transfer inefficiency of BCCD is a jump function of signal charge quantity. The profile of a spot tail under laser radiation is simulated using this self-developed model. The simulation results are compared with experimental findings to validate this model.

Effects of proton and neutron irradiation on dark signal of CCD

The proton and neutron irradiation and annealing experiments are carried out on a domestic buried channel CCD (charge-coupled devices), Monte Carlo method being applied to calculate the energy deposition of scientific CCD irradiated by proton and neutron, and the radiation damage mechanism of the device is analyzed. The displacement damage dose in N+ buried channel is simulated. During irradiation and annealing experiments, the main parameter (dark signal) is investigated. Results show that the dark signal of the buried channel CCD irradiated by 10 MeV proton and 1 MeV neutron rises obviously. With the same fluence, the increase of dark signal and the displacement damage dose in N+ buried channel caused by 10 MeV proton is larger than that by 1 MeV neutron. Dark signal caused by proton irradiation is divided into surface dark signal and bulk dark signal. Oxide-trapped-charges and interface states may be caused by ionization-generated surface dark signal, and the bulk defects may be caused by displacement-generated bulk dark signal. Neutron irradiation only affects the bulk dark signal. Defects and their annealing temperature are studied. The dark signal of CCD irradiated by proton is greatly reduced after annealing, this phenomenon means that the dark signal is mainly affected by ionization. The proportion of bulk dark signals in total dark signals can be calculated by the remainder of dark signal after annealing, and it is at most about 20% or less. From the formula, the position of energy level of bulk defects has an obvious influence on the bulk dark signal. The energy level in the middle of the forbidden band can provide effective hot carriers. Combining the results of experiment and simulation, when the displacement damage doses in N+ buried channel are the same, the bulk dark signal produced by proton is nearly the same as that produced by neutron. This phenomenon means that the defect levels in the forbidden band gap caused by proton and neutron irradiation have the same contributions to dark signal generation. Effect of proton and neutron irradiation on the bulk dark signal is homogeneous. The displacement damage dose can be used to characterize the degradation degree of the bulk dark signal in CCD after irradiation.

Study of CCD Transport on CMOS Imaging Technology: Comparison Between SCCD and BCCD, and Ramp Effect on the CTI

This paper presents measurements performed on charge-coupled device (CCD) structures manufactured on a deep micrometer CMOS imaging technology, in surface channel CCD and in buried channel CCD mode. The charge transfer inefficiency is evaluated for both CCD modes with regard to the injected charge, and the influence of the rising and falling time effect is explored. Controlling the ramp and especially reducing its abruptness allows to get much lower charge transfer inefficiency in buried CCD mode. On the contrary, we did not observe any effect of the ramp on surface channel CCD mode because of the presence of interface traps at the silicon-oxide interface.

Simulation for signal charge transfer of charge coupled devices

Physical device models and numerical processing methods are presented to simulate a linear buried channel charge coupled devices (CCDs). The dynamic transfer process of CCD is carried out by a three-phase clock pulse driver. By using the semiconductor device simulation software MEDICI, dynamic transfer pictures of signal charges cells, electron concentration and electrostatic potential are presented. The key parameters of CCD such as charge transfer efficiency (CTE) and dark electrons are numerically simulated. The simulation results agree with the theoretic and experimental results.

Measurement of the Dα spectrum produced by fast ions in DIII-D

Fast ions are produced by neutral beam injection and ion cyclotron heating in toroidal magnetic fusion devices. As deuterium fast ions orbit around the device and pass through a neutral beam, some deuterons neutralize and emit D(alpha) light. For a favorable viewing geometry, the emission is Doppler shifted away from other bright interfering signals. In the 2005 campaign, we built a two channel charge-coupled device based diagnostic to measure the fast-ion velocity distribution and spatial profile under a wide variety of operating conditions. Fast-ion data are acquired with a time resolution of approximately 1 ms, spatial resolution of approximately 5 cm, and energy resolution of approximately 10 keV. Background subtraction and fitting techniques eliminate various contaminants in the spectrum. Neutral particle and neutron diagnostics corroborate the D(alpha) measurement. Examples of fast-ion slowing down and pitch angle scattering in quiescent plasma and fast-ion acceleration by high harmonic ion cyclotron heating are presented.

3-Dimensional Numerical Analysis of Deep Depletion Buried Channel MOSFETs and CCDs

The visual analysis of buried channel (BC) devices such as buried channel MOSFETs and CCDs (Charge Coupled Devices) is investigated to give better understanding and insight for their electrical behaviours using a 3-dimensional (3-D) numerical simulation. This paper clearly demonstrates the capability of the numerical simulation of EVEREST for characterising the analysis of a depletion mode MOSFET and BC CCD, which is a simulation software package of the semiconductor device. The inverse threshold and punch-through voltages obtained from the simulations showed an excellent agreement with those from the measurement involving errors of within approximately 1.8% and 6%, respectively, leading to the channel implanted doping profile of only approximately 4-5% error. For simulation of a buried channel CCD an advanced adaptive discretising technique was used to provide more accurate analysis for the potential barrier height between two channels and depletion depth of a deep depletion CCD, thereby reducing the CPU running time and computer storage requirements. The simulated result for the depletion depth also showed good agreement with the measurement. Thus, the results obtained from this simulation can be employed as the input data of a circuit simulator.

MCT heteroepitaxial 4 × 288 FPA

4 × 288 heteroepitaxial mercury–cadmium telluride (MCT) linear arrays for long wavelength infrared (LWIR) applications with 28 × 25 micron diodes and charge coupled devices (CCD) silicon readouts were designed, manufactured and tested. MCT heteroepitaxial layers were grown by MBE technology on (0 1 3) GaAs substrates with CdZnTe buffer layers and had cutoff wavelength λ co≈11.8±0.15 μm at T=78 K. To decrease the surface influence of carrier recombination processes the compositionally dependent layers with increase of Cd content both toward the surface and HgCdTe/CdZnTe boundary interface were grown. Silicon readouts with CCD multiplexers with input direct injection circuits were designed, manufactured and tested. The testing procedure, to qualify readout integrated circuits on wafer level at T=300 K, was worked out. The silicon readouts for 4 × 288 arrays, with skimming and partitioning functions included were manufactured by n-channel MOS technology with buried or surface channel CCD register. The HgCdTe arrays and Si CCD readouts were hybridized by cold welding indium bumps technology. With skimming mode used for 4 × 288 MCT n–p-junctions, the detectivity for several tested 4 × 288 arrays was within D λ ∗≅9×10 10–1.8×10 11 cm Hz 1/2/W for background temperature T b=295 K.

Random line selected charge accumulation readout structure for random access infrared imager application

A 512×512 monolithic platinum silicide focal plane array with random line selection was proposed. The device was modified from an interline transfer charge couple device configuration by adapting a random line selected charge accumulation structure on a vertical register and four-tap readout structure on a horizontal register to achieve a high fill factor, high charge handling capacity, and high frame rate operation. An on-chip 9-bit decoder was used to select a particular line to transfer charges to their associated vertical charge coupled device (CCD) register. Accompanied with the vertical reset drain circuitry, 1–512 lines can be selected and read out by the vertical CCD registers. The dummy charges on the unselected lines are then transferred to the vertical CCD channel and dumped to the vertical reset drain. In this unique readout structure, a frame rate of upto 240 frames/s can be obtained to select 128×128 of Schottky barrier detectors for 5 MHz clock frequency operation. By changing the selection pattern on a 9-bit decoder, the device can be operated in either interlaced or non-interlaced format, and the charge integration time can be varied which results in variable exposure control. This architecture not only maintains the advantages of CCD structure for its low noise and excellent signal to noise ratio, but also provides readout capability of any portion of the array like MOS structure does.

Charge transfer efficiency in proton damaged CCD's

We have performed detailed measurements of the charge transfer efficiency (CTE) in a thinned, backside-illuminated imaging charge-coupled device (CCD). The device had been damaged in three separate sections by proton radiation typical of that which a CCD would receive in space-borne experiments, nuclear imaging, or particle detection. We examined CTE as a function of signal level, temperature, and radiation dose. The dominant factor affecting the CTE in radiation-damaged CCD's is seen to be trapping by bulk states. We present a simple physical model for trapping as a function of transfer rate, trap concentration, and temperature. We have made calculations using this model and arrived at predictions which closely match the measured results. The CTE was also observed to have a nonlinear dependence on signal level. Using two-dimensional device simulations to examine the distribution of the charge packets in the CCD channel over a range of signal levels, we were able to explain the observed variation.

A 9-b charge-to-digital converter for integrated image sensors

Charge-to-digital conversion offers advantages over conventional charge readout techniques because it performs digitization directly in the charge domain. The approach consolidates hardware, reduces power and weight, and eliminates many sources of noise and nonlinearity. This paper introduces an architecture for a charge-to-digital converter (CDC) that is tailored toward a charge-coupled device (CCD) implementation. New methods of generating charge, sensing charge, and comparing charge packets are described that improve conversion accuracy. Factors limiting device performance are discussed. Measured results are presented for two prototype CDCs. The first, using buried channel CCDs, is optimized for resolution. It achieves 56 dB spurious free dynamic range (SFDR) at a 2 MHz sampling rate and operates from 5 V. The second, using surface channel CCDs, is optimized for power and speed. It achieves 49 dB SFDR at a 15 MHz sampling rate and consumes 13 mW power at its maximum sampling rate of 22 MHz.

CCD soft X-ray imaging spectrometer for the ASCA satellite

We describe the development of a charge-coupled device (CCD) array for use as a soft X-ray (0.4-12 keV) imaging spectrometer for the ASCA (formerly Astro-D) satellite. The CCDs are 420/spl times/420-pixel frame-transfer devices designed to be closely abutted to other chips on three sides of the imaging array. The imagers are made on 6500-/spl Omega//spl middot/cm p-type float-zone silicon for depletion depths of about 50 /spl mu/m under typical CCD bias conditions. The read noise of the CCD is typically 3-4 e/sup /spl minus// rms at data rates of 50 KHz resulting in an energy resolution E//spl delta/E/spl ap/50 at 5.9 keV. The complete focal-plane sensor consists of a 2/spl times/2 array of these devices mounted on a common substrate. Radiation damage from energetic protons is mitigated by the use of a narrow potential trough along the center of the CCD channel to confine the small X-ray event charge to a reduced volume and thereby minimize trapping effects. Charged-particle events from the non-X-ray space background are minimized by using a junction on the back of the chip to deplete most of the neutral bulk and draw background charge away from the CCD. Wafer-level device screening at low temperatures and the focal-plane packaging methods are also described. >

Power dissipation in frame-transfer charge-coupled devices

The power dissipation for large-area high-speed charge-coupled device (CCD) arrays is analyzed. The four mechanisms responsible for power dissipation in a CCD are carrier lift and friction within the CCD channel, load currents through the on-chip output amplifiers, capacitive charge and discharge currents through the epitaxial layer or substrate, and currents flowing through the polysilicon clock register electrodes. These processes are easily calculated for small or slow devices. For large high-speed devices, on the other hand, the conventional analytical techniques are inadequate. The large device area leads to high resistive-capacitive constants in the parallel clock registers, causing clock pulses to degrade in shape as they travel along a clock electrode. A distributed system analysis based on lumped circuit parameters for each pixel is necessary to calculate the current and thus the power dissipated at each point on the surface of the COD. A computer simulation of a standard frame-transfer CCD was performed using SPICE software. The results of the simulation indicate a much lower power dissipation than previously assumed and also point out various problems with conventional device architectures for large-area high-speed CCDs.

Ionizing radiation hardening of a CCD technology

A three-level polysilicon, buried channel charge coupled device (CCD) technology has been tested for Co/sup 60/ ionizing radiation damage up to a total dose of 90 krad(Si). For this purpose CCD image sensors have been irradiated together with their associated test structures. These include different types of MOSFETs, natural transistors, buried channel transistors, field transistors, and diodes. The devices have been fully characterized during irradiation and afterwards, as a function of time. The standard technology has been assessed, leading to the implementation of process and design modifications. The modified technology has been further tested according to the same procedure and significant improvement in the sensors' behavior under irradiation and during annealing has been observed. The radiation hardness of the CCDs has been correlated with the results of the test structures, allowing a better understanding of the degradation phenomena and of the countermeasures needed for a radiation-hardened technology. >

Buried channel charge-coupled device on gas-source MBE grown InP

The first epitaxial-channel InP CCDs on semi-insulating substrates have been demonstrated using gas-source MBE grown layers. Channel isolation was achieved using a mesa etch, and the two level overlapping gate structure was insulated using indirect plasma enhanced CVD grown SiO2. Initial results indicate stale device operation with charge transfer efficiencies, at 1–3MHz operating frequencies, of ∼0.99.

A CCD Delay Line for Video Applications

A surface channel Charge-Coupled Device is used for delaying one television line. The chip uses 4 analog-multiplexed lines and has on-chip circuits for adapting to clock frequencies that can occur in various types of video equipment. The 4.8mm2 chip requires only 40 mW from a 5 volt supply.

On the charge-handling capacity of epitaxial and ion-implanted GaAs buried channel charge-coupled devices

The charge-handling capacity of GaAs B.C.C.D.'s has been studied on the basis of the numerical solution of the 1-D and 2-D Poisson equations. Epitaxial and ion-implanted channels have been considered for two kinds of devices, respectively Schottky or M.I.S. gate B.C.C.D.'s. After having defined bulk storage conditions, we have showed that a 3-phase system and Schottky gate B.C.C.D. allow to store the more important signal-charge. A double implant channel structure is proposed to overcome the contact of the carriers with the interface in ion-implanted channel B.C.C.D. For both kinds of devices, the charge capacity increases when the channel doping concentration (or the dose) and when the channel thickness (or the implantation range) are reduced.

Rejection characteristics in a video-signal processor using CCD comb filters

This paper describes charge-coupled device (CCD) combfilter rejection characteristics in the video bandwidth. Notch-frequency shifts and rejection-ratio decreases are caused by the incomplete charge transfer in the CCD channel and also by timing error in the charge sampling, which shorten the effective delay time from the ideal 1 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">H</tex> period. In the 1H comb filters, 30-dB rejections are achieved within the 4.5-MHz bandwidth for less than 2 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-5</sup> per transfer inefficiency. The timing error in the input section can be compensated for by adjusting the input-gate biasing voltage. The analyses are extended to the 2 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">H</tex> comb filter constructed with three identical CCD's. The 1.2 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-4</sup> inefficiency, which is six times as large compared with that in the 1 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">H</tex> filter, is allowable to maintain the 30-dB ratio. The rejection is shown to be constant when the product of the inefficiencies in the series-connected CCD's is constant. The experimentally obtained results suggest the analyses are reasonable.

Control of boron diffusion in polysilicon for constructing overlapping polysilicon gate charge-coupled devices

The diffusion coefficient of boron having values significantly different in silicon and silicon dioxide has been used to control the doping of boron impurity in intrinsic polysilicon deposited over the gate oxide. The method reduces the possibility of doping gate oxide while diffusing boron in polysilicon. Using the method, silicon gate p-MOSFETS and twenty bit photo-sensor, four phase, double overlapping polysilicon gate surface channel charge-coupled devices have been constructed with a transfer efficiency of 0.9990. The measured values of the threshold voltage of MOSFETS are in close agreement with their corresponding calculated values.