Cell Transistor Research Articles

Thickness scaling limitation factors of ONO interpoly dielectric for nonvolatile memory devices

This paper describes the scaling limitation factors of ONO interpoly dielectric thickness, mainly considering the charge retention capability and threshold voltage stability for nonvolatile memory cell transistors with a stacked-gate structure, based on experimental results. For good intrinsic charge retention capability, either the top- or bottom-oxide thickness should be greater than around 6 nm. On the other hand, a thicker top oxide structure is preferable to minimize degradation due to defects. It has been confirmed that a 3.2 nm bottom-oxide shows detectable threshold voltage instability, but 4 nm does not. Effective oxide thickness scaling down to around 13 nm should be possible for flash memory devices with a quarter-micron design rule.

Associating CMOS transistors with BDD arcs for technologymapping

A novel BDD class that allows a direct association of CMOS transistors with BDD arcs is proposed. This BDD class, terminal suppressed BDDs (TBDDs), allows a direct technology mapping, with the aim of automatic leaf cell generation. This is obtained from a straightforward extraction of the cell transistor topology from a TBDD.

An automatic temperature compensation of internal sense ground for subquarter micron DRAM's

This paper describes DRAM array driving techniques and the parameter scaling techniques for low voltage operation using the boosted sense ground (BSG) scheme and further improved methods. Temperature compensation and adjustable internal voltage levels maintain a small subthreshold leakage current for a memory cell transistor (MC-Tr), and a distributed BSG (DBSG) scheme and a column decoded sensing (CDS) scheme achieve the effective scaling. These schemes can set the DRAM array free from the leakage current problem and the influence of temperature variations. Therefore, parameters for the MC-Tr, threshold voltage (V/sub th/), and the boosted voltage for the gate bias can be scaled down, and it is possible to determine the V/sub th/ of the MC-Tr simply (0.45 V at K=0.4) for the satisfaction of the small leakage current, for high speed and stable operation, and for high reliability (V/sub PP/ is below 2 V/sub CC/). They are applicable to subquarter micron DRAM's of 256 Mb and more.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A 30-ns 256-Mb DRAM with a multidivided array structure

A 256-Mb DRAM with a multidivided array structure has been developed and fabricated with 0.25- mu m CMOS technology. It features 30-ns access time, 16-b I/Os, and a 35-mA operating current at a 60-ns cycle time. Three key circuit technologies were used in its design: a partial cell array activation scheme for reducing power-line voltage bounce and operating current, a selective pull-up data-line architecture to increase I/O width and reduce power dissipation, and a time-sharing refresh scheme to maintain the conventional refresh period without reducing operational margin. Memory cell size was 0.72 mu m/sup 2/. Use of the trench isolated cell transistor and the HSG cylindrical stacked capacitor cells helped reduce chip size to 333 mm/sup 2/.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Speed optimised array architecture for flash EEPROMs

The author describes a new architecture for a split-gate flash EEPROM memory array. The new array architecture provides increased speed and less susceptibility to soft writes during read operations. A unique circuit design and operation method obviates the need for applying high erase voltage in the path between the memory array and the sense amplifier. This allows all the transistors in this speed path to be fabricated as low voltage minimum channel length devices, thereby increasing their speed of operation and consequently the speed of the memory device as a whole. The new architecture, however, requires the addition of two extra rows of nonmemory cell transistors in addition to following a strict programming sequence to guard against spurious programming of unselected cells

Directory and Trace memory chip with active discharge cell

The Directory and Trace memory chip is a 7.1Kb static random-access memory with 28-bit field simultaneous compare function and independent read and write 28-bit field addressing. The array is organized as four 64 by 28 subarrays. It incorporates a unique Schottky barrier diode (SBD)-coupled cell with active discharge. As memory cells are reduced in size with each new generation, soft errors become a major concern. One method of providing high soft-error immunity is to operate the memory cell transistors in the saturation region. However, in order to write data into such memory cells, the saturation capacitance in the memory cell transistors must be discharged. In prior art, such a capacitive transistor-saturation discharge was accompanied by increased power consumption and/or delay. Typically, the new data signals themselves are used to overcome this saturation capacitance. In this design a unique SBD-coupled active discharge cell discharges the conducting transistor saturation capacitance before writing new data into the cell. Thus, it enhances the write performance and preserves the high soft-error immunity of the cell.

DRAM cell characterization by AC-impedance measurement

A novel characterization technique for DRAM test cell arrays is presented. The new method permits the extraction of subthreshold IV-characteristics of the cell transistor and its threshold voltage with no DC contacts to the source. The DRAM cell is viewed as an equivalent circuit of resistors and capacitors, whose values can be determined by sweeping the frequency of the AC-impedance bridge. Using this technique, it is possible to characterize the cell transistor in its natural habitat without resorting to special test structures.

GaAs/AlGaAs dynamic random access memory cell

A single-transistor dynamic random access memory circuit using a GaAs/AlGaAs structure as the storage cell and modulation-doped field-effect transistors for memory accessing and output sensing has been developed. The functionality of the memory is demonstrated and a storage time of 5.4s is measured at room temperature.

Simple and efficient modeling of EPROM writing

A simple and efficient model for first-order simulation of the writing of n-channel erasable programmable ROM (EPROM) cells is presented. It allows the current injected into the gate insulator of the cell transistor to be calculated, accounting (at first order) both for the nonMaxwellian form of the electron energy distribution and for the nonlocal nature of carrier heating. The model is implemented as a postprocessor of a two-dimensional device simulator, and it is validated by means of a comparison with experimental data obtained with devices with effective channel lengths ranging from 1.4 to 0.5 mu m. >

Soft-error characteristics in bipolar memory cells with small critical charge

The alpha-particle-induced soft-error mechanism in a high-speed bipolar static RAM (SRAM) which is used for mainframe computers is investigated using a three-dimensional (3-D) device and a circuit simulator. It is shown that a constant critical charge for the memory cell does not exist. This is because the memory cell's soft-error sensitivities to the charges collected at the base and collector of the cell transistor are different due to the difference in time constants of the base and collector. To take into account this sensitivity difference in the soft-error rate simulation, an effective-charge model is proposed. This model incorporates weight coefficients that express the memory cell's soft-error sensitivities to the charges collected at the base and collector. Accelerated soft-error rates of the 4-kb SRAMs are simulated using the effective-charge model. >

A diagonal active-area stacked capacitor DRAM cell with storage capacitor on bit line

A stacked-capacitor (STC) cell concept for 16-Mb DRAMs is introduced. The STC cell features a storage capacitor placed on a bit line and a diagonal active area. This enables a large storage capacitance, 35 fF/b, to be achieved on a 3.36- mu m/sup 2/ cell. By eliminating completely the structural interferences between bit line and plate electrode, the storage-node pattern is maximized. The STC cell also features low noise characteristics due to its shielded bit-line structure. This minimizes the interbit-line capacitance to below 1% of the bit-line capacitance in the memory array. The average charge retention time, measured using an experimental 2-kb array, is 30 s at 40 degrees C. The characteristics of the diagonal active memory cell transistor are comparable to those of a conventional transistor. >

ESD phenomena in graded junction devices: C. Duvvury, R. N. Rountree, H. J. Stiegler, T. Polygreen and D. Corum. 27th a. Proc. IEEE/IRPS Int. Reliab. Phys. Symp., 71 (1989)

A non-uniform lateral boron profile along the channel width is observed in a buried-channel p-MOSFET and a memory cell transistor when BF2 implantation is applied at the dose of ∼1013 cm−2 to form a channel. SIMS profile analysis and two-dimensional simulation results show that this abnormal profile is formed by transient enhanced diffusion (TED) due to BF2 implantation damage during gate oxidation process. It is found that RTA process just prior to the gate oxidation is useful to eliminate the TED of boron so that inverse narrow width effect, short channel effect and threshold voltage fluctuation are remarkably improved in a buried-channel p-MOSFET. In addition, the RTA process can also reduce BF2 implantation dose without decreasing threshold voltage by the suppression of boron diffusion in a cell transistor. Therefore, the retention time of DRAM can be enhanced by reducing space charge region field in a cell transistor due to lower boron concentration compared with a conventional device.

A 256‐K 13‐nanosecond CMOS SRAM

AbstractRecently, many types of very high‐speed static RAMs (SRAM) using CMOS or BiCMOS technologies have been announced. Even with CMOS SRAMs, which operate in the range of 10 ns access time, both device and circuit technologies and also usage and reliability problems become prominent, and must be solved in order to achieve adequate speed performance.This paper discusses technical problems and their realistic solutions for achieving very‐high speed SRAMs using CMOS from the viewpoint of device and circuit technologies. Consequently, short channel MOSFETs using 1.0 μm NMOS and 1.0 μm PMOS gate lengths were used to reduce the access time. In order to reduce the soft‐errors that cause problems when high‐speed SRAMs are operated with a short cycle time, the Vth of memory cell transistors is set higher than the level in the other circuits. Hence, the soft‐error rate is the same when the device is operated with a longer cycle time.With respect to circuit technology, a high sensitivity sense amplifier is used with a smaller gain decrease under low voltage, a circumstance which is suitable to high‐speed SRAMs that are sensitive to supply voltage bounce due to electrical noise within the chip.In order to implement systems using high‐speed SRAMs, a write‐timing control circuit is introduced, which alleviates the timing constraints on the address skew during write timing. Utilizing these technologies with a CMOS process, a 256‐K SRAM with an access time of 13 ns has been achieved.

High efficiency crystalline silicon solar cells

Based recombination at residual defect and impurity recombination centers is identified to be the likely cause of the 20% (AM 1) efficiency barrier in the highest efficiency silicon solar cells reported to date. To reach the 20% (AM 1) efficiency, base recombination must be further reduced by either stress-free and clean fabrication techniques on high lifetime crystals or novel base structure design, such as the graded thin-base back-surface-field structure proposed and analyzed by Sah and Lindholm. To break the 20% barrier, residual base recombination losses must be eliminated and emitter recombination must be reduced. Several novel emitter designs to reduce recombination losses have been proposed and one demonstrated. These involve the reduction of emitter interface recombination losses at the non-contact surface by high quality thermal oxide and at the metal-contact/silicon-emitter interface by either a thin tunneling oxide, as demonstrated by Green, or by a polysilicon barrier layer between the metal conductor and the silicon emitter surface. An efficiency of 23.8% (AM 1) has been estimated using Neugroschel's data on emitter interface recombination velocity and dark current density of polysilicon barrier layers. Novel floating emitter or non-contact emitter solar cell transistor structures have also been proposed by Sah and Cheng to reduce emitter recombination loss for >20% efficient silicon solar cells.

SDW MOSFET static memory cell

The single device well (SDW) memory cell, including an access transistor, uses only two SDW MOSFETs, versus four-to-six transistors in conventional static memory cells and thus a great saving in silicon area results. Cell static and dynamic performance are discussed and simulated using an appropriate model implemented in the computer-aided circuit analysis program WATAND. The access time of the new cell is comparable to that of conventional MOSFET cells. Using 3 /spl mu/m technology, an SDW memory cell consumes an area of 600 /spl mu/m/SUP 2/ and has an average power consumption of 10 /spl mu/W at 5 V supply. Another version of the cell using a polyresistor is also discussed.

Implementation of ternary identity cells using c.m.o.s. integrated circuits

Most of the ternary operators recently described are based on the identity cell and realised by c.m.o.s. integrated circuits. Three simpler designs of the identity cell are presented here: the 2-transistor inverter, the improved-speed 6-transistor cell and the all-c.m.o.s. micropower cell using only 12 transistors.

A new circuit configuration for a static memory cell with an area of 880 /spl mu/m/sup 2/

A new 5-transistor memory cell in double polysilicon technology with depletion-load elements and a minimum linewidth of 3 /spl mu/m is presented. The circuit configuration, based on a Schmitt trigger, leads to static memory cells having a bit density of 1100 bit/mm/SUP 2/ and an average power consumption of 5.5 /spl mu/W/cell. With the help of computer simulations the static and dynamic behavior of the basic circuit are calculated and discussed in detail as well as the two possible operation modes of the memory cell. These results compare favorably with the experimental results obtained on a realized 2/spl times/4 memory array. The performance of the proposed memory cell is the same as that of a conventional 6-transistor cell, but the area is reduced.