Abstract
The alpha-particle-induced soft-error mechanism in a high-speed bipolar static RAM (SRAM) which is used for mainframe computers is investigated using a three-dimensional (3-D) device and a circuit simulator. It is shown that a constant critical charge for the memory cell does not exist. This is because the memory cell's soft-error sensitivities to the charges collected at the base and collector of the cell transistor are different due to the difference in time constants of the base and collector. To take into account this sensitivity difference in the soft-error rate simulation, an effective-charge model is proposed. This model incorporates weight coefficients that express the memory cell's soft-error sensitivities to the charges collected at the base and collector. Accelerated soft-error rates of the 4-kb SRAMs are simulated using the effective-charge model. >
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