Cell Transistor Research Articles

Analysis of functional failure mode of commercial deep sub-micron SRAM induced by total dose irradiation

Functional failure mode of commercial deep sub-micron static random access memory (SRAM) induced by total dose irradiation is experimentally analyzed and verified by circuit simulation. We extensively characterize the functional failure mode of the device by testing its electrical parameters and function with test patterns covering different functional failure modes. Experimental results reveal that the functional failure mode of the device is a temporary function interruption caused by peripheral circuits being sensitive to the standby current rising. By including radiation-induced threshold shift and off-state leakage current in memory cell transistors, we simulate the influence of radiation on the functionality of the memory cell. Simulation results reveal that the memory cell is tolerant to irradiation due to its high stability, which agrees with our experimental result.

Built-in self-test for bias temperature instability, hot-carrier injection, and gate oxide breakdown in embedded DRAMs

As CMOS technology scales, frontend wearout mechanisms, such as bias temperature instability, hot-carrier injection, and gate oxide breakdown significantly degrade transistor performance. We investigate the impact of these frontend wearout mechanisms on embedded DRAM cells, which are used for last-level caches owing to their high-density characteristics. Our results show that a cell transistor of eDRAM is more susceptible to gate oxide breakdown than bias temperature instability and hot-carrier injection. The impact of all such wearout mechanisms on a cell capacitor is negligible. Based on observations from our simulations, which estimate the performance degradation of eDRAMs resulting from frontend wearout mechanisms, we propose monitoring methods to proactively detect the failures of eDRAMs caused by frontend wearout mechanisms.

The influence of medium conductivity on ECIS measurements with field‐effect transistor arrays

Field‐effect transistors (FETs) offer a well‐known biosensor platform for many years now. In most of the applications, FETs are used as potentiometric sensors. In earlier studies, we used FETs for cell‐substrate impedance sensing and showed that in this way, the well‐known electric cell‐substrate impedance sensing (ECIS) method can be scaled down to a single cell resolution. When using new sensor types for ECIS, new coupling models for data interpretation are also needed. In this study, the influence of the conductivity of the measurement buffer and its effect on the recorded spectra was investigated. Human embryonic kidney cells were cultured on the FET surfaces and their impedance spectra were measured. By fitting the data to an established electrically equivalent circuit model, changes in the relevant cell parameters can be obtained. The derived cell‐related data offer an advanced understanding in cell transistor interface modeling.

Defect elimination in solid-phase crystallised Si thin films by line-focus diode laser annealing

A high density of intragrain defects in solid-phase crystallised Si thin films results in poor electronic properties and impedes their use for thin-film solar cell or thin-film transistor applications. This paper demonstrates that a high-power line-focus diode laser can eliminate intragrain defects (microtwins and dislocations) in polycrystalline Si films while maintaining the smooth defect-free surface. Improved electronic properties of ultra-thin polycrystalline Si thin films are thus achieved. To alleviate crack formation during diode laser annealing, a rapid-thermal pre-treatment at 800°C for 60s is introduced since it effectively relieves the tensile stress in the films and thus generates a more stable precursor material for subsequent laser annealing. The film thickness plays an important role in diode laser annealing. The films thinner than 100nm show relatively smaller improvement due to the limited absorption of 808nm laser radiation.

Adaptive Technique for Overcoming Performance Degradation Due to Aging on 6T SRAM Cells

The threshold voltage drifts induced by positive bias temperature instability (PBTI) and negative bias temperature instability (NBTI) weaken nMOS and pMOS, respectively. These long-term aging threshold voltage drifts degrade SRAM cell stability, margin, and performance. This paper presents a low area overhead adaptive body bias (ABB) circuit that compensates BTI aging effects and also improves performance of an aged SRAM cell. The proposed circuit uses a control circuit and word line voltage to control the voltage applied to the body of 6T SRAM cell's transistors such that the BTI effect dependence of threshold voltage is reduced. In the worst case, the proposed ABB reduces the HOLD SNM degradation by 6.85%, the READ SNM degradation by 12.24%, the WRITE margin degradation by 2.16%, the READ delay by 28.68%, and the WRITE delay by 32.61% compared to the conventional SRAM cell at 108 s aging time.

Statistical Analysis of Read Static Noise Margin for Near/Sub-Threshold SRAM Cell

A fast statistical method for the analysis of the Read SNM of a 6 T SRAM cell in near/subthreshold region is proposed. The method is based on the nonlinear behavior of the cell. DIBL and body effects are thoroughly considered in the derivation of an accurate closed form solution for the Read Static Noise Margin (SNM) of the near/subthreshold SRAM cell. This method uses the state space equation to derive the Read SNM of the cell as a function of threshold voltage of cell transistors. This function shows the dependency of the Read SNM on sizing, VDD, temperature, and threshold voltage variations. It provides a fast reliability analysis for a cell array of a given size and a supply voltage. It also calculates the accurate value of failure probability of the cell. The analytical results are verified using Monte-Carlo simulations in 45 nm Predictive Technology Models.

Effects of Material Morphology on the Performance of Organic Electronics

The fast-growing organic electronics field has received the attention of a lot of researchers because of its wide applicability in the consumer electronics, photovoltaics and biotechnology. Since the charge transport, absorption of electromagnetic radiations and exciton migration in the organic semiconductors is direction dependent, it is mandatory to control the morphology and orientation of the active layer with respect to the applications. So, in this review we have briefly discussed the role of thin film morphology on the organic solar cell and organic field-effect transistor performance. And the efforts have been taken by the researchers to control the morphology of thin films through the active layer engineering and molecular engineering are summarized.

Advanced Si solid phase crystallization for vertical channel in vertical NANDs

The advanced solid phase crystallization (SPC) method using the SiGe/Si bi-layer structure is proposed to obtain high-mobility poly-Si thin-film transistors in next generation vertical NAND (VNAND) devices. During the SPC process, the top SiGe thin film acts as a selective nucleation layer to induce surface nucleation and equiaxial microstructure. Subsequently, this SiGe thin film microstructure is propagated to the underlying Si thin film by epitaxy-like growth. The initial nucleation at the SiGe surface was clearly observed by in situ transmission electron microscopy (TEM) when heating up to 600 °C. The equiaxial microstructures of both SiGe nucleation and Si channel layers were shown in the crystallized bi-layer plan-view TEM measurements. Based on these experimental results, the large-grained and less-defective Si microstructure is expected to form near the channel region of each VNAND cell transistor, which may improve the electrical characteristics.

Investigation of ISFET device parameters to optimize for impedimetric sensing of cellular adhesion

In this study we describe how we were able to use an equivalent‐electrical circuit for the cell–transistor contact to optimize a future chip design for better performance in cell–substrate adhesion experiments. From our simulations we found that higher capacitances of the source and drain contact lines are able to shift the cell adhesion effects to more moderate frequencies in the range of up to 200 kHz. For larger cell–substrate adhesion effects, the transconductance value of the FET devices needs to be increased as well. We used these simulation results to design a new generation of FET devices. These devices were successfully fabricated in our clean room facilities. In electronic cell–substrate adhesion experiments this new generation of devices showed superior performance compared to an earlier version. Most importantly, our new devices have now an almost flat topology enabling future single‐cell migration experiments. HEK293 cells adhered with a flat morphology to a newly fabricated FET sensor device (scale bar 50 µm)

Modeling the characteristics of trigger elements of two-phase CMOS logic, taking into account the charge sharing effect under exposure to single nuclear particles

The fault tolerance of CMOS D and RS flip-flops with a two-phase structure and memory cells based on them under exposure to single nuclear particles depends on the response to charge collection by several nodes. The relation between pairs of nodes with identical critical characteristics and specifics of symmetry of electric couplings between trigger transistors was established for DICE and Quatro cells. Critical pairs of nodes with minimal critical charges and an increased noise immunity were determined. The guidelines for mutual arrangement of transistors in DICE cells were given. The examples of quantitative estimation of critical dependences were given for cells with a 65 nm bulk CMOS design rule. DICE cells have an advantage in the event of multiple influence on the nodes.

Low-Power Multiport SRAM With Cross-Point Write Word-Lines, Shared Write Bit-Lines, and Shared Write Row-Access Transistors

This brief proposes one-write-one-read (1W1R) and two-write-two-read (2W2R) multiport (MP) SRAMs for register file applications in nanoscale CMOS technology. The cell features a cross-point Write word-line structure to mitigate Write Half-Select disturb and improve the static noise margin (SNM). The Write bit-lines (WBLs) and Write row-access transistors are shared with adjacent bit-cells to reduce the cell transistor count and area. The scheme halves the number of WBL, thus reducing WBL leakage and power consumption. In addition, column-based virtual VSS control is employed for the Read stack to reduce the Read power consumption. Post-sim results show that the proposed scheme reduces both Write/Read current consumption by over 30% compared with the previous MP structure. The proposed scheme is demonstrated and validated by an 8-Kb 2W2R SRAM test chip fabricated in TSMC 40-nm CMOS technology.

InAlN/GaN HEMTs based L-band high-power packaged amplifiers

This paper presents power results of L-band packaged hybrid amplifiers using InAlN/GaN/SiC HEMT power dies. The high-power densities achieved both in pulsed and continuous wave (cw) modes confirm the interest of such technology for high-frequency, high-power, and high-temperature operation. We present here record RF power measurements for different versions of amplifiers. Up to 260 W, i.e. 3.6 W/mm, in pulsed (10 µs/10%) conditions, and 105 W, i.e. 2.9 W/mm, in cw conditions were achieved. Such results are made possible thanks to the impressive performances of InAlN/GaN transistors, even when operating at high temperatures. Unit cell transistors deliver output powers of 4.3 W/mm at Vds = 40 V in the cw mode of operation at the frequency of 2 GHz. The transistor process is described here, as well as the amplifiers design and measurements, with a particular focus to the thermal management aspects.

FN-degradation of S-RCAT with different grain size and oxidation method

Sphere-shaped-recess-cell-array-transistor (S-RCAT) has played a major role in the sub-80nm design-rule DRAM. The Fowler–Nordheim (FN) degradation of gate oxide in S-RCAT has been studied with the gate electrode grain size and gate oxidation method. Negative shift of threshold voltage and increase of sub-threshold swing in NMOS cell transistor were observed under certain process conditions. As the grain size of gate poly-Si decreases, the negative shift of threshold voltage and increase of sub-threshold swing were decreased. In addition the negative shift perfectly disappeared in the radical oxidation instead of the thermal oxidation. It is assumed that the negative shifts of threshold voltage and the possibility of hole-trap originate from the curvature of energy band bending of S-RCAT. From our study, the electric filed in the recessed channel transistor must be reduced by the small grain sized electrode, and the radical oxidation which has low interface-trap is suitable for 3D-transistors.

In situ indium-induced crystallisation of low temperature nano-poly silicon (LTNPS) thin film on ITO glass substrate

For the first time, the low temperature nano-poly silicon (LTNPS) thin films were formed on indium tin oxide (ITO) glass with a temperature of ~200ºC using the in situ indium-induced crystallisation of the plasma enhanced CVD (PECVD) deposited a-Si. Compared with the conventional method for transfer of the PECVD formed amorphous structure to the nano-poly one, the technology features a low temperature operation, and without an extra high temperature (300ºC) post-deposition annealing (PDA). Thus the LTNPS can be applied for solar cell or thin film transistor in flexible substrates pre-coated by ITO film. We used SEM, XRD and Raman to characterise the deposited films, and interpret the growing mechanisms in details.

Implications of the Logical Decode on the Radiation Response of a Multi-Level Cell NAND Flash Memory

The radiation response of a multi-level cell (MLC) NAND flash is used to determine the organization of logical states as they correspond to floating gate charge levels of constituent bit cell transistors. This “logical decode” is then used to demonstrate how an MLC device can be used to emulate a single-level cell (SLC) flash with total dose radiation sensitivity equivalent to and even surpassing that of a comparable actual SLC device. In addition, it is shown that the logical decode must be taken into account when performing radiation testing on MLC flash devices so as to gather accurate worst case response data.

Process Variation-Aware Nonuniform Cache Management in a 3D Die-Stacked Multicore Processor

Process variations in integrated circuits have significant impact on their performance, leakage, and stability. This is particularly evident in large, regular, and dense structures such as DRAMs. DRAMs are built using minimized transistors with presumably uniform speed in an organized array structure. Process variation can introduce latency disparity among different memory arrays. With the proliferation of 3D stacking technology, DRAMs become a favorable choice for stacking on top of a multicore processor as a last level cache for large capacity, high bandwidth, and low power. Hence, variations in bank speed create a unique problem of nonuniform cache accesses in 3D space. In this paper, we investigate cache management techniques for tolerating process variation in a 3D DRAM stacked onto a multicore processor. We modeled the process variation in a four-layer DRAM memory, including cell transistor, capacitor trench, and peripheral circuit, to characterize the latency and retention time variations among different banks. As a result, the notion of fast and slow banks from the core's standpoint is no longer associated with their physical distances with the banks. They are determined by the different bank latencies due to process variation. We develop cache migration schemes that utilize fast banks while limiting the cost due to migration. Our experiments show that there is a great performance benefit in exploiting fast memory banks through migration. On average, a variation-aware management can improve the performance of a workload over the baseline (where one of the slowest bank speed is assumed for all banks) by 16.5 percent. We are also only 0.8 percent away in performance from an ideal memory where no process variation is present.

New SRAM design using body bias technique for low‐power and high‐speed applications

ABSTRACTIn this paper, a new SRAM cell with body‐bias actively controlled by a control circuit and word line is introduced to realize low‐power and high‐speed applications. The cell uses two word lines, which vary between positive and negative voltage levels to control the body bias of cell's transistors. In this design, using a peripheral control circuit with the least possible number of transistors, the access time is decreased and also a trade‐off between static and dynamic power consumption is provided. Compared to a conventional SRAM cell, the proposed cell reduces the static power consumption by 82% and improves the read performance by 40% and the write performance by 27%. Copyright © 2013 John Wiley & Sons, Ltd.

Ultra Low Power 6T SRAM Cell Designed on 65nm Low Power Technology Platform Suitable for High Temperature Applications

Cell leakage (Istby) reduction of ultra low power (ULP) SRAM with conventional 6T configuration on 65nm low power (LP) technology platform is studied in the paper. Istby components are analyzed and optimized for the leakage reduction by adopting no sleep transistor or other leakage suppression schemes. Gate oxide of cell transistor is grown thicker compared to 65nm LP process to fully suppress the gate oxide leakage contribution. Sub-threshold leakage of the cell transistors are much decreased to lower down both the total Istby and its temperature sensitivity. The 16M ULP SRAM featuring a 0.525um2 bit cell size with the proposed technique shows Istby as low as 1.2pA/bit at 1.2V under room temperature and 3.1pA/bit at 85℃. The voltage data retention (VDR) of the ULP SRAM is shown to be 0.7V indicating the feasibility of Istby further reduction by applying low Vdd under stand by mode. Moreover, the ULP process is fully compatible with logic process flow, by adopting several more masks, the above mentioned SRAM can be embedded into standard CMOS flow easily.

Dependence of DRAM Device Performance on Passivation Annealing Position in Trench and Stack Structures for Manufacturing Optimization

The dependence of dynamic random access memory (DRAM) device performance on trench and stack cell structures was first observed by changing the process position of passivation annealing. For the trench DRAM, the data retention fail bit counts (FBCs) decreased by 18% and the cell transistor threshold voltage (CTVth) shift by 53 mV. The FBCs are primarily influenced by the junction leakage current. In contrast, for the stack DRAM, the data retention FBCs increased by 225% and the CTVth shift increased by 20 mV. The FBCs are primarily influenced by the gate-induced drain leakage (GIDL) current because of the large gate and the drain overlap region in the recess channel array transistor (RCAT). The interface states increased after the deposition of the plasma nitride layer, as observed in the charge pumping measurement in the trench DRAM. Transmission electron microscopy indicated that the gate oxide thickness in the bottom region of the RCAT is thinner to generate gate oxide leakage. Furthermore, a decrease in the activation energy from 0.64 to 0.55 eV implies the occurrence of GIDL current, which corresponds to the FBC analysis result. This paper demonstrated that the passivation annealing position requires careful adjustment for device and manufacturing optimization.

Analysis of Single-Trap-Induced Random Telegraph Noise on FinFET Devices, 6T SRAM Cell, and Logic Circuits

This paper analyzes the impacts of single-charged-trap-induced random telegraph noise (RTN) on FinFET devices in tied- and independent-gate modes, 6T static random access memory (SRAM) cell stability, and several basic logic circuits. The dependence of RTN on trap location, EOT, and temperature is evaluated through 3-D atomistic TCAD simulation. It is observed that the charged trap located near the bottom of sidewall (gate) interface and in the middle region between the source and drain will result in the most significant impact. EOT scaling and higher operating temperature improve the immunity to RTN. RTN degradation in independent-gate mode and the dependence on the location of the trap and bias-dependent current-conduction path are analyzed. We show that the planar BULK device, with larger subthreshold swing ( <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$S.S.$</tex></formula> ) and comparable trap-induced <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$V_{T}$</tex></formula> shift, exhibits less nominal RTN degradation than FinFET for traps placed in the worst position. However, the larger variability and surface conduction characteristic of the planar BULK device lead to broader dispersion and larger worst case RTN degradation than the FinFET device with smaller variability and volume conduction. For traps randomly placed across the interface, similar RTN amplitude dispersions are observed for FinFET and planar BULK devices except in the vicinity of distribution tail due to the strong interaction between the charged trap and discrete random dopants in planar BULK devices. For 6T FinFET SRAM cell, the READ static noise margin of 64 possible combinations from trapping/detrapping in each cell transistor is examined. Because of reduced carriers with decreasing supply voltage <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$(V_{\rm dd})$</tex></formula> , the importance of RTN on subthreshold cell stability increases. Moreover, the leakage and delay of FinFET inverters, two-way nand, and two-to-one multiplexer are investigated using 3-D TCAD mixed-mode simulations. The RTN is found to cause <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\sim$</tex></formula> 24%–27% and <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\sim$</tex></formula> 13%–15% variations in leakage and delay at <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$V_{ \rm dd} = \hbox{0.4}\ \hbox{V}$</tex></formula> , respectively, for the logic circuits evaluated.