Abstract
As CMOS technology scales, frontend wearout mechanisms, such as bias temperature instability, hot-carrier injection, and gate oxide breakdown significantly degrade transistor performance. We investigate the impact of these frontend wearout mechanisms on embedded DRAM cells, which are used for last-level caches owing to their high-density characteristics. Our results show that a cell transistor of eDRAM is more susceptible to gate oxide breakdown than bias temperature instability and hot-carrier injection. The impact of all such wearout mechanisms on a cell capacitor is negligible. Based on observations from our simulations, which estimate the performance degradation of eDRAMs resulting from frontend wearout mechanisms, we propose monitoring methods to proactively detect the failures of eDRAMs caused by frontend wearout mechanisms.
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