Frontend wearout modeling from device to system with power/ground signature analysis

Abstract

With the scaling of CMOS technology, frontend wearout mechanisms, including Bias Temperature Instability (BTI) and Gate Oxide Breakdown (GOBD), are serious issues for transistors. In general, degradation due to BTI and GOBD are modeled based on test structure data, and the models are expressed by a threshold voltage shift and a voltage dependent ohmic resistance in the circuit simulation. In this paper, we determine the relationship between the threshold voltage shift model and ground signal degradation for BTI, and the oxide degradation model and the ground/power signal degradation for GOBD. The calculation of amplitude and delay shift of the signature signal is used to find the relationship. Then, we find a mathematical model to calculate the degradation of a chip. Also, based on the combined models, we extract the critical path and calculate the system lifetime.