Negative Bias Temperature Instability and Gate Oxide Breakdown Modeling in Circuits With Die-to-Die Calibration Through Power Supply and Ground Signal Measurements

Abstract

With the scaling of CMOS technology, negative bias temperature instability (NBTI) and gate oxide breakdown (GOBD) are serious issues for transistors. Normally, degradation due to NBTI and GOBD are modeled based on test structure data during process development and monitored with embedded test structures in product die. In this paper, we present a method to determine NBTI and GOBD model parameters through I/O measurements. This work targets products that do not include embedded test structures for wearout monitoring. The ground and power supply bounce signals are used for the calculation of delay and amplitude shifts, which in turn estimate threshold voltage shifts due to NBTI and leakage resistance decreases from gate dielectric degradation. From this data, the NBTI and GOBD parameters are estimated. We calculate the lifetime for each chip individually using calibrated NBTI and GOBD models. The methodology enables the extraction of NBTI and GOBD model parameters for individual chips, not just for the manufacturing process, and hence it becomes possible to differentiate chips that are more or less vulnerable to NBTI and GOBD.