System-level estimation of threshold voltage degradation due to NBTI with I/O measurements

Abstract

With the scaling of CMOS technology, Negative Bias Temperature Instability (NBTI) and Process Variations (PV) are serious issues for transistors. Normally, degradation due to NBTI is modeled based on test structure data or ring oscillators embedded within product die. In this paper, we present a method to determine the initial average channel length (L) and threshold voltage (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</inf> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sup> ) for individual chips, together with NBTI model parameters through I/O measurements. We determine a relationship between ΔV <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</inf> , V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</inf> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sup> , L and ground signal variation and fit models to the simulation results. The voltage of the ground signal is used for the calculation of the delay and amplitude shifts which are used to extract PV and NBTI parameters. Then, we calculate the lifetime for each chip individually using calibrated NBTI models, accounting for process variations. The methodology enables the extraction of NBTI and PV model parameters for individual chips, not just for the manufacturing process, and hence it becomes possible to differentiate chips that have different parameters initially and are more or less vulnerable to NBTI.