Extraction of threshold voltage degradation modeling due to Negative Bias Temperature Instability in circuits with I/O measurements

Abstract

Negative Bias Temperature Instability (NBTI) is a serious reliability issue for pMOS transistors. Normally, degradation due to NBTI is modeled based on test structure data or ring oscillators embedded within product die. In this paper, we present a new method to determine the NBTI model parameters through I/O circuit measurements. We determine a relationship between Δ V th and signature signal degradation and fit a model to the simulation results. The signature signal involves the calculation of the degradation in the voltage signature, measured as delay and amplitude shifts. Given an estimate of Δ V th we find NBTI model parameters. Then, using the NBTI parameters at test conditions, we scale to use conditions and calculate lifetime. The methodology enables the extraction of NBTI model parameters for individual chips, not just for the manufacturing process, and hence it becomes possible to identify chips that are more vulnerable to NBTI.