Ultra-Thin High-K Dielectric Profile Based NBTI Compact Model for Nanoscale Bulk MOSFET

Abstract

Negative Bias Temperature Instability (NBTI) is a key reliability and consistency issue for ultra-scaled Silicon IC technology with substantial consequences on both analog and digital circuit design For nano devices, NBTI apparently increases the threshold voltage exponentially on transient platform consequently, decreases the drain current and transconductance in the similar manner. The threshold voltage recovery function manifests the logarithmic transient reliance. The issue is of critical perturb, especially in p-channel nanoscale MOS devices, as these devices generally operate with negative gate-to-source voltage Use of high-K dielectric stack enhances the NBTI impact on these nano devices The manuscript investigates and models the NBTI characteristics for bulk driven nanoscale p-MOS device with ultrathin high-K gate dielectric stack. The gate terminal is transiently negatively biased and further relaxed with positive bias conditions for ample time for the recovery of the initial characteristics. Threshold voltage shift at various gate bias conditions and diverse temperatures demonstrate that NBTI is highly subjugated by the defect generation and hole trapping bustle in gate dielectric pre-existing traps NBTI recovery is accelerated by increasing the temperature. Threshold voltage shift in recovery phase showed a swift initial transient, ensued by an acutely sluggish, passive non-exponential transient. A compact NBTI model for nano MOSFET is proffered capturing the dependency of stress phase gate bias, recovery gate voltage and operating temperature Importantly, only the restricted bunch of fitting parameters are required for anticipation. The proposed NBTI model is valid for FD/SOI/FinFET technology also and can be easily implemented on TCAD circuit simulators.