CIC Filter Research Articles

Off-Axis Integral Cavity Carbon Dioxide Gas Sensor Based on Machine-Learning-Based Optimization.

Accurately detecting atmospheric carbon dioxide is a vital part of responding to the global greenhouse effect. Conventional off-axis integral cavity detection systems are computationally intensive and susceptible to environmental factors. This study deploys an Extreme Learning Machine model incorporating a cascaded integrator comb (CIC) filter into the off-axis integrating cavity. It is shown that appropriate parameters can effectively improve the performance of the instrument in terms of lower detection limit, accuracy, and root mean square deviation. The proposed method is incorporated successfully into a monitoring station situated near an industrial area for detecting atmospheric carbon dioxide (CO2) concentration daily.

Automated design of embedded digital signal processing systems on SOC platform

The object of the study is the procedures for automated design and analysis of digital signal processing algorithms on the SoC technology platform. The subject of the study is models, methods and procedures for designing and optimal selection of SoC components for the implementation of digital signal processing algorithms for audio spectrum. The aim of the study is to develop models and procedures for determining the possibilities of a compromise distribution of signal processing algorithm computations in the cycle of computer-aided design on the SoC technology platform in terms of performance and the feasibility of using hardware and software algorithms realization. The article solves the following tasks: consideration of the procedures for interacting the processor core with programmable logic as part of system-on-chip systems; development of procedures for computer-aided design and analysis of signal processing systems using programming languages and hardware description languages for the implementation of embedded systems. The following methods are being used: implementation of digital signal processing algorithms in the C programming language and high-level synthesis tools for realizing IP blocks, diagnostic experiment by generating test signal patterns, and analysis of the processing results at the system output. The results achieved. Based on the analysis of the procedures for the interaction of the processor core and programmable logic on the selected SoC platform, a model of the audio spectrum signal processing system is designed. The practical implementation was performed based on the Vivado/Vitis/Vitis HLS CAD tool stack. The proposed model was verified using a programmable test signal generator and analyzing the obtained characteristics of digital filters at the system output. Conclusions. The article analyzes the principles of designing embedded information processing systems implemented in system-on-chip. The principles of building and analyzing digital signal processing systems based on system-on-chip containing programmable logic and processor parts are considered. The developed methods have been tested on the algorithms of CIC and FIR filters on the technological platform of SoC FPGA of the ZYNQ-7000 family of Xilinx company.

Design and Implementation of Digital Down Converter for WiFi Network

This paper introduces a field-programmable gate array (FPGA)-based digital down converter (DDC) processing a sampling frequency of about 3.64 GHz to a down-converted frequency of 28.4375 MHz to match the IEEE 802.11ah Wi-Fi HaLow standard. The proposed DDC uses a polyphase mixer(PM) and a resampling filter. The PM adopts parallel coordinate rotation digital computer (CORDIC) processors and lowpass filter arrays to reduce high-speed data rates with minimum resource utilization. Again, the resampling filter employs a cascaded integrator comb (CIC) filter associated with a parallel prefixed adder (PPA) and a multi-channel systolic finite impulse response (FIR) filter implemented with canonical expression, attaining optimum hardware cost. Converting floating-point to fixed-point data types provides significant resource savings. Finally, the improved design is coded in the Xilinx Vivado synthesis tool and successfully tested on the FPGA Kintex-7 device. In contrast to other recent architectures, the proposed design substantially reduces area requirements and power utilization. The Matlab tool verifies the design to achieve an acceptable spurious-free dynamic range (SFDR) of 115 dB.

Design of a Sigma-Delta Analog-to-Digital Converter Cascade Decimation Filter

As the current mainstream high-precision ADC architecture, sigma-delta ADC is extensively employed in a wide range of domains and applications. This paper presents the design of a highly efficient cascaded digital decimation filter for sigma-delta ADCs, emphasizing the suppression of high folding band noise and the achievement of a flat passband. Additionally, this study addresses the critical balance between filter performance and power consumption. An inserting zero (IZ) filter is incorporated into a cascaded integrator comb (CIC) filter to enhance aliasing suppression. The IZ filter and compensation filter are optimized using the particle swarm optimization (PSO) algorithm to achieve greater noise attenuation and smaller passband ripple. The designed filter achieves a noise attenuation of 93.4 dB in the folding band and exhibits an overall passband ripple of 0.0477 dB within a bandwidth of 20 KHz. To decrease the power consumption in the filter design, polyphase decomposition has been applied. The filter structure is implemented on an FPGA, processing a 5-bit stream from a 64-times oversampling rate and third-order sigma-delta modulator. The signal-to-noise ratio (SNR) of the output signal reaches 91.7 dB. For ASIC design, the filter utilizes 180 nm CMOS technology with a power consumption of 0.217 mW and occupies a layout area of 0.72 mm2. The post-layout simulation result indicates that the SNR remains at 91.7 dB.

Multistage Decimator Design for the Low-PHY PRACH Receiver

This paper describes the design of a multistage decimator for the Physical Random Access Channel (PRACH) receiver based on the hybrid time/frequency domain architecture. Flexible structure of the multistage decimator allows to support all combinations of PRACH subcarrier spacings and carrier bandwidths defined in the 3rd Generation Partnership Project (3GPP) Release 15 for Frequency Range (FR) 1. Impulse responses of low pass filters for each decimation stage do not depend on a selected combination allowing to facilitate hardware implementation. The multistage decimator jointly uses the Cascaded Integrator-Comb (CIC) and Nyquist filters to minimize number of required multipliers. Acceptable degradation level due to decimation in the receiver performance is estimated based on requirements defined by the Radio Access Network (RAN) working group 4. Assuming no specific detection algorithm, it is shown that the proposed design introduces negligible degradation, less than 0.1 dB in the operating Signal-to-Noise Ratio (SNR) region.

Design and FPGA Implementation of Compensator for Sharpening CIC Filter

This paper presents a novel compensator design for sharpened CIC (cascade-integrator-comb) proposed in the literature. Sharpened CIC provides higher aliasing attenuation than the CIC filter. However, its passband droop is higher than the corresponding CIC filter and must be compensated. Our motivation was to design a decimator with better compensation than the one proposed in the literature. The proposed decimation filter has two coefficients and six adders. The coefficients are determined using particle swarm optimization (PSO) in MATLAB. Two designs are presented. The first one has two multipliers and six adders. The second is a multiplierless design obtained by presenting optimal coefficients in the signed power-of-two (SPT) form. The proposed design is compared with the design from the literature. The designed compensator is implemented in a field-programmable gate array (FPGA). Details of the implementation are described in the paper.

Design and Implementation of High Speed Low Power Decimation Filter for Hearing AID Applications

This work is focused on designing and implementing a decimation filter specifically intended for use in hearing aid applications. The filter utilizes distributed arithmetic (DA) and is described in this brief. Our proposal involves the development of a reconfigurable finite impulse response (FIR) filter, which utilizes both offset binary code (OBC) and binary distributed arithmetic (DA) techniques. Additionally, we utilize canonic signed digit (CSD) representation to develop decimation filters, which include the CIC filter, half band filter, and corrector filter. In this work, we have implemented a decimation filter using Matlab Simulink. We have utilized Xilinx Vivado 19.2 to execute the FIR filters, binary DA filters, and OBC DA-based filters. Our focus is on implementing these filters using VLSI architecture, in order to achieve low power consumption, reduced latency, less area, and fast speed.

Implementation of polyphase digital down converter for wireless applications

This paper briefs the hardware-efficient polyphase digital down converter (DDC), which reduces the input sampling frequency to 3.64 GHz and produces a complex output to meet the IEEE 802.11ah wireless network standard. The design comprises a polyphase mixer (PM) filter and a lowpass polyphase finite impulse response (PFIR) filter. The PM filter uses a cascaded integrator comb (CIC) decimation filter based on multiplexer technology to potentially process parallel input interfaces and considerably reduce the sampling rate. The time-sharing mechanism of the CIC filter performs an efficient hardware implementation. Again, the improved design technique of the PFIR filter can effectively increase the operating speed and optimize power consumption. The proposed design offers high flexibility due to programmable sampling rate factors that can support multistandard communication systems. In addition, the design includes the truncation mechanism to protect against overflow errors and the fixed-point data type in each filter node to minimize the area requirements. The presented polyphase DDC is tested using the field-programmable gate array (FPGA) platform targeting the Xilinx Kintex-7 device. According to experimental results, the described DDC significantly reduces the logical resources and power dissipation associated with earlier design structures. The functional verification is tested to ensure the validation of the suggested design.

Design of Low Power Temperature Sensor Based on 180 nm Complementary Metal Oxide Semiconductor Technology

CMOS temperature sensor is widely used in power monitoring system, power consumption is an important index. The digital filter power consumption is one of the main sources of the temperature sensor power consumption, and limiting the Digital filter power consumption becomes an important method to realize the low power consumption of the temperature sensor. Based on this, a low power digital filter for CMOS temperature sensors is designed, and a precision adaptive digital filter is proposed, the filter is cascaded by a recursive CIC filter and a FIR filter based on a shift adder, the order of CIC filter and FIR filter can be adjusted according to the difference between the measured temperature and the threshold temperature range set by the user, when the measured temperature is outside the threshold temperature range, the operation unit in the filter is selectively switched off, which makes the power consumption of the filter decrease. For the temperature range that does not need to be monitored, the requirement of temperature measurement accuracy is usually not high, if high-precision temperature monitoring is still carried out, it will have a lot of unnecessary power consumption, in this paper, an adaptive precision digital filter is used to solve the problem. In order to further reduce the power consumption of the temperature sensor, according to the characteristics of the slow change of the temperature signal, a single temperature conversion combined with idle off mode is adopted, the FIR filter power consumption is reduced by 5.5% by optimizing the single temperature conversion operation. The temperature sensor is realized by 180 nm CMOS process. The results show that the sensor can achieve an accuracy of 0.47 °C in the temperature range of −55–115 °C when the measured temperature is in the threshold temperature range, under 1.8 V supply voltage, the power consumption of the digital part of the sensor is 20.15 μw. When the measured temperature is outside the threshold temperature range, the power consumption of the digital part of the sensor can be reduced by 11.3%.

Simplifying Zero Rotations in Cascaded Integrator-Comb Decimators [Tips & Tricks

Simplifying Zero Rotations in Cascaded Integrator-Comb Decimators [Tips & Tricks

Design and Implementation of Sigma-Delta ADC Filter

This paper presents a digital decimation filter based on a third-order four-bit Sigma-Delta modulator. The digital decimation filter is an important part of the Sigma-Delta ADC and is designed to make the Sigma-Delta ADC (Analog-to-Digital Converter) meets the requirements of Signal-to-Noise Ratio (SNR) not less than 120 dB and Equivalent Number of Bits (ENOB) not less than 20 bits. It adopts a three-stages cascaded structure including a Cascaded Integrator Comb (CIC) decimation filter, a Finite Impulse Response (FIR) compensation filter, and a half-band (HB) filter. This structure effectively reduces about 13% multiplier cells and memory cells. The coefficient symmetry technique and CSD (Canonic Signed Digit) coding technique are used to optimize the parameters of the filter, which further reduces the computational complexity. After optimization, the circuit area is reduced by about 15%, and the logic resources are decreased by about 23%. The Verilog hardware description language is used to describe the behavior of the digital decimation filter, and the simulation is carried out based on the VCS (Verilog Compile Simulator) platform. At the same time, the prototype verification is implemented on the Xilinx Artix-7 series FPGA, and the ADC achieves 113 dB SNR and 18.5 bits ENOB. Finally, the Sigma-Delta ADC is fabricated on SMIC 0.18 μm CMOS process with the layout area of 714.8 μm × 628.4 μm and the power consumption of 11.2 mW. The more tests for the fabricated prototypes will be performed in the future to verify that the Sigma-Delta ADC complies with the design specifications.

A Sensorless Control Strategy for Permanent Magnet Synchronous Motor at Low Switching Frequency

The high-frequency (HF) square-wave voltage injection method can be used in permanent magnet synchronous motor (PMSM) drive systems. However, when the switching frequency is too low, the injection frequency will also decrease, which will reduce the update frequency of the HF response current, making it difficult to extract the position quadrature signal and affecting the accuracy of position estimation and control performance. This paper proposes a method for extracting position quadrature signals based on sampling rate transformation, and a signal processing strategy based on Cascade Integrator Comb (CIC) interpolation filtering, which can solve the problem of waveform distortion caused by the low sampling rate of the extracted position quadrature signal. This strategy can increase the sampling rate of the position quadrature signal to the pulse width modulation (PWM) update frequency by interpolating in the sampling current, thereby reducing the harmonic content of the position quadrature signal and improving the position estimation. precision. In addition, the PWM update frequency and estimated rotational speed information are used to compensate for the delay caused by position estimation and inverter update, which effectively improves the accuracy of position estimation. Finally, the effectiveness of the proposed control strategy is verified by simulation.

Optimum multiplierless sharpened cascaded-integrator-comb filters

Cascaded-integrator-comb (CIC) filter provides high folding-band attenuation within a narrow band. To make this filter suitable for processing of wideband signals, its amplitude response is often improved by using polynomial sharpening, resulting in so-called sharpened CIC (SCIC) filter. In this paper, the authors propose a method for global optimization of multiplierless SCIC filters. The method is based on the maximization of minimum folding-band attenuation, assuming the coefficients of sharpening polynomial are the sums of signed-power-of-two (SPT) terms. Filter's structure is controlled by bounding the maximum word length of polynomial coefficients and the maximum number of terms in the entire sharpening polynomial. The proposed method supports an arbitrary choice of passband edge frequency. The filters obtained employ a low number of SPT terms to achieve folding-band attenuations which are close to those obtained by real-valued polynomial coefficients.

Design and Implementation of Decimation Filter for 13-bit Sigma-Delta ADC Based on FPGA

A 13 bit Sigma-Delta ADC for a signal band of 40K Hz is designed in MATLAB Simulink and then implemented using Xilinx system generator tool. The first order Sigma-Delta modulator is designed to work at a signal band of 40 KHz at an oversampling ratio (OSR) of 256 with a sampling frequency of 20.48 MHz. The proposed decimation filter design is consists of a second order Cascaded Integrator Comb filter (CIC) followed by two finite impulse response (FIR) filters. This architecture reduces the need for multiplication which is need very large area. This architecture implements a decimation ratio of 256 and allows a maximum resolution of 13 bits in the output of the filter. The decimation filter was designed and tested in Xilinx system generator tool which reduces the design cycle by directly generating efficient VHDL code. The results obtained show that the overall Sigma-Delta ADC is able to achieve an ENOB (Effective Number Of Bit) of 13.71 bits and SNR of 84.3 dB.

A Power-Efficient Multichannel Low-Pass Filter Based on the Cascaded Multiple Accumulate Finite Impulse Response (CMFIR) Structure for Digital Image Processing

The author offers a power-efficient multichannel low-pass filter for digital image processing based on the cascade multiple accumulate finite impulse response (CMFIR) structure in this study. The CMFIR filter was created using the outputs of a linear time-invariant system (LTI), which was built using a cascaded integrator comb (CIC) and a MAC low-pass filter. The sample rate convertor based on CIC filters effectively conducts decimation or interpolation. The sample rate convertor with the CIC filter can only accommodate narrowband transmissions and so cannot be utilized for wideband signals. The MAC architecture-based sample rate convertor is a good solution for high-bandwidth signals, but it uses more resources like registers and flip-flops, which increases power consumption. Here, the CMFIR low-pass filter acts as an interpolator, introducing a sample to boost the image's resolution. CMFIR is a useful tool for addressing the issue of aliasing during sampling. In addition, the genetic algorithm was used to increase the filter's resource utilization and power consumption efficiency.

Alternative Data Paths for the Cascaded Integrator-Comb Decimator [Tips & Tricks

Alternative data paths for the cascaded integrator-comb (CIC) decimator are presented that can be derived upon applying one or two modifications. In the first modification, the integrator-comb pair that surrounds the downsampling register is replaced by a simpler Integrate-and-Dump (ID) block that performs the same decimation task. The resulting data path is referred to as CIC-ID. In the second modification, the remaining comb filters are replaced by a timemultiplexed comb, and the resulting data path is referred to as CIC-ID-TMUX. Compared with a classic N-stage CIC, CIC-ID saves one arithmetic unit and one register, whereas CIC-ID-TMUX uses the same number of registers but trades (N - 1) arithmetic units for a simpler two-to-one multiplexer. Both CIC-ID and CIC-ID-TMUX perform slightly fewer arithmetic operations per output sample because of the absence of the comb filter absorbed by the ID block. Pruning formulas for both architectures are presented along with implementation details.

Efficient design of decimation filter using linear programming and its FPGA implementation

In this paper we present two-stage CIC (cascaded-integrator-comb) decimation filters with decimation factor M expressed as M = M1M2, where M1,M2∈Z+. The proposed decimator-I aims to minimize the pass-band droop using a cascade connection of Kaiser Hamming (KH) and Saramäki-Ritoniemi (SR) sharpening structures. The coefficients of second stage are determined using linear programming in MATLAB. The proposed CIC decimator-I when designed for various integer decimation factors on an average has a pass-band droop of −0.09 dB at the normalized frequency of 1/2 M and an average alias rejection of −44 dB at the normalized frequency of 3/2 M. Further, another decimator-II structure extends decimator-I to achieve an alias rejection of −87 dB and pass-band droop of −0.17 dB. The FPGA implementation of proposed designs has lower slice utilization and achieves higher maximum operating frequency than other existing competing designs. The performance of proposed decimation filters is confirmed using computer simulations in analog-to-digital converters (ADC) and sigma-delta (ΣΔ) modulators.

Sampling Rate Optimization for Improving the Cascaded Integrator Comb Filter Characteristics

The cascaded integrator comb (CIC) filters are characterized by coefficient less and reduced hardware requirement, which make them an economical finite impulse response (FIR) class in many signal processing applications. They consist of an integrator section working at the high sampling rate and a comb section working at the low sampling rate. However, they don’t have well defined frequency response. To remedy this problem, several structures have been proposed but the performance is still unsatisfactory. Thence, this paper deals with the improvement of the CIC filter characteristics by optimizing its sampling rate. This solution increases the performance characteristics of CIC filters by improving the stopband attenuation and ripple as well as the passband droop. Also, this paper presents a comparison of the proposed method with some other existing structures such as the conventional CIC, the sharpened CIC, and the modified sharpened CIC filters, which has proven the effectiveness of the proposed method.

Design and comparative analysis of on-chip sigma delta ADC for signal processing applications

Advent in VLSI technology made digital signal processing to take over analog signal processing. Analog to digital converter plays a vital role in modern digital signal processing applications. Various signal processing applications incorporated sigma delta ADC among different analog to digital converters because of its digital dominant architecture. This paper presents the design of a low pass continuous time sigma delta analog to digital converter on-chip architecture with a very few passive components connected externally to FPGA suitable for signal processing applications, wireless application, sonar and radar beamforming. Schematic level architecture of high speed comparator working at a differential swing which is not allowed by FPGA standard differential pads is designed. By applying various differential swings at the input to LVPECL, the performance and power is analyzed. High performance comparator schematic is designed as on-chip continuous-time sigma-delta analog to digital converter architecture. SPICE simulations are carried out to verify the maximum input frequency for given RC values. Xilinx provided Spartan 6 I/O pad and package SPICE models are used. Power analysis is carried out with LVPECL logic family based differential buffers along with external RC circuit. The analog and digital sections simulations along with mixed signal simulations at different stages are performed. Power and performance analysis are carried out using h-Spice and questasim simulations. schematic level architecture of a high speed comparator at a differential swing of 1.65 ± 1.5 V which is not allowed by standard differential pads is designed. Analysis illustrates that proposed on-chip continuous-time sigma-delta analog to digital converter exhibits a sampling rate of 400 MHz designed with high speed comparator with varied differential swing. Power analysis resulted with 1.86 mW for an input signal of 1 MHz. Optimal filtering is achieved with total decimation of 400, out of which the decimation of 100 is achieved by CIC filter and PFIR filter achieves remaining decimation factor of 4. Output data rate of 1 MHz with a dynamic range of 72 dB is achieved with less bill of material that suites for signal processing applications.

Design and Implementation of a Farrow-Interpolator-Based Digital Front-End in LTE Receivers for Carrier Aggregation

A digital front-end decimation chain based on both Farrow interpolator for fractional sample-rate conversion and a digital mixer is proposed in order to comply with the long-term evolution standards in radio receivers with ten frequency modes. Design requirement specifications with adjacent channel selectivity, inband blockers, and narrowband blockers are all satisfied so that the proposed digital front-end is 3GPP-compliant. Furthermore, the proposed digital front-end addresses carrier aggregation in the standards via appropriate frequency translations. The digital front-end has a cascaded integrator comb filter prior to Farrow interpolator and also has a per-carrier carrier aggregation filter and channel selection filter following the digital mixer. A Farrow interpolator with an integrate-and-dump circuitry controlled by a condition signal is proposed and also a digital mixer with periodic reset to prevent phase error accumulation is proposed. From the standpoint of design methodology, three models are all developed for the overall digital front-end, namely, functional models, cycle-accurate models, and bit-accurate models. Performance is verified by means of the cycle-accurate model and subsequently, by means of a special C++ class, the bitwidths are minimized in a methodic manner for area minimization. For system-level performance verification, the orthogonal frequency division multiplexing receiver is also modeled. The critical path delay of each building block is analyzed and the spectral-domain view is obtained for each building block of the digital front-end circuitry. The proposed digital front-end circuitry is simulated, designed, and both synthesized in a 180 nm CMOS application-specific integrated circuit technology and implemented in the Xilinx XC6VLX550T field-programmable gate array (Xilinx, San Jose, CA, USA).