CIC Filter Research Articles

A class of selective CIC FIR filter functions

A new class of modified selective multiplerless Cascaded-Integrator-Comb (CIC) finite impulse response (FIR) Alter functions with application in modern communication systems, which have superior performances compared to the classical CIC Alter functions are presented here. A few design examples that illustrate the properties of the proposed filter class are also presented. Novel filter functions have a minimum attenuation of 166.52 dB, 258.56 dB and 350.46 dB, respectively. The achieved improvements versus classical CIC Alters are 29.84 dB, 34.90 dB and 39.82 dB, respectively.

DDC Design for Multi-Frequency Receiver Based on RF Sampling

Multi-frequency receivers rely on GNSS to achieve high-precision positioning, high sensitivity and other functions. GNSS signal frequencies are widely distributed around 1.1GHz to 1.6GHz. Good performance RF front-end receiver will provide high-quality acquisition and tracking environment, reducing the SER to ensure CNR. RF sampling technique is widely used in software radio for its simple structure, flexible configuration, and other advantages, but rarely used in satellite navigation, because the high signal carrier frequency and sampling rate, down-conversion based on RF sampling becomes a big challenge. So, to solve the problems of widely distributed we design three signal bands, using different local oscillator to implement signal down-conversion; to solve the problems of high sampling rate, we propose a down-conversion program of using a cascade of CIC filter’s ployphase and FIR compensation filter. Through the simulation of MATLAB after tracking tests, analysis of CNR and other indicators of programs. Ultimately, we implement the program with Verilog language on the multi-frequency GNSS receiver. The results show that this scheme can achieve digital down-conversion and stable performance of tracking loop with less consumption of resources.

Design of selective CIC filter functions

The aim of this letter is to provide graphs which can be used to design a novel class of selective CIC (Cascaded-Integrator–Comb) filters given insertion loss specification. The goal is to choose the free integer filter parameters such that the filter function yields a desired frequency response. To determine the filter parameters needed to satisfy the desired specifications, one can use the graphs of normalized passband and stopband cut-off frequencies versus filter order N. Two graphs, one for maximum attenuation in the passband and one for minimum attenuation in the stopband, are given here. Achieved improvement of performances of the novel class of CIC filter functions over the classical CIC filters is also given. In case of N=7, the novel class of CIC filter functions gives improvements of 27.68dB, 47.29dB and 66.53dB for different values 1, 2 and 3 of free parameter L, respectively.

Real-Time Processing of Multifrequency Eddy Currents Testing Signals: Design, Implementation, and Evaluation

The design, implementation, and evaluation of a real-time digital signal processing architecture to generate and process multifrequency signals for eddy currents testing is described in this paper. This architecture is implemented on a dedicated instrument whose processing core is a field-programmable gate array. Stimulus generation is achieved using direct digital synthesis with some important improvements to reduce spurious frequency components. An in-phase and in-quadrature demodulation scheme is implemented to estimate the real and imaginary parts of the probe output signal. A cascaded integrator comb decimator is used to lower the sampling frequency and then allow narrowband filtering with low resources. The proposed architecture is able to generate and process the stimulus and input data at 125 MSamples/s and to estimate the input data components at 1.25 MSamples/s rate for eddy-currents with multiple simultaneous testing frequencies between 2.5 kHz and 10 MHz. Experimental validation is performed using a set of synthetic defects and two stimulus with different spectral composition.

NOVEL FPGA DESIGN AND IMPLEMENTATION OF DIGITAL UP CONVERTER

In our world, communication systems play an importa nt role in day to day life. In wireless and wired c ommunication systems, signals are to be upsampled at the transmitter. Digital up converter (DUC) is a sample rate conversion techniq ue which is widely used to increase the sampling rate of an input signal. The digital up converter converts low sampled digital b aseband signal to a pass band signal. In this paper, we are going to design and i mplement a low noise digital up converter on a FPGA (Field Programmable Gate Array). In digital up converter, the input signal i s filtered and converted to higher sampling rate an d then it is modulated with the carrier signal generated from the direct digital sy nthesizer (DDS). This system consists of a cascaded integrator comb (CIC) interpolation filter, cascaded integrator comb comp ensation filter, multiplier and a direct digital synthesizer. The cascaded integrator comb interpolation filter performs upsampling of th e input signal and the cascaded integrator comb com pensation filter is used to compensate the losses of CIC filter by filtering th e input signal. The multiplier is used for multiply ing the upsampled signal from CIC filter with the carrier signal generated from DDS a nd gives the DUC output. In this DUC, the input si gnal is upsampled at the rate of eight. Here, two digital up converters are used and connected with an adder in order to obtain a low n oise output signal. The coding of this work is done in VHDL. The simulation and fu nctional verification is carried out using Xilinx I SE and FPGA implementation is carried out using Virtex 5.

A single die 1.2 V 55 to 95 dB DR delta sigma ADC with configurable modulator and OSR

A single die 1.2 V multi-stage noise shaping (Mash) 2-2 delta sigma analog to digital converter (ADC) for wide applications is implemented. The configurable Mash 2-2 modulator with a new decimation filter design is presented to achieve wide and high dynamic range (DR) for multiple practical applications. The novel modulator can be configured as a Mash 2-2 modulator for high precision or a 2-order modulator for low DR. The decimation filter is designed to select the OSR flexibly among cascaded integrator comb (CIC) filter and two half-band filters (HBF). The serial peripheral interface (SPI) can be used to adjust the sampling frequency and the oversampling ratio (OSR). The design was fabricated in a 0.13 μm CMOS process with an area of 0.91 mm2 and a total power of 5.2 mW. The measurement results show that the dynamic range (DR) of the proposed ADC can change from 55 to 95 dB with the configurable OSR from 16 to 256. The spurious free dynamic range (SFDR) and signal-to-noise distortion ratio (SNDR) can get 99 dB and 86.5 dB, respectively.

On design of a novel class of selective CIC FIR filter functions with improved response

The Cascaded-Integrator-Comb (CIC) filter is a non-recursive (FIR) filter which is multiplier free, consisting only of two building blocks (simple integrator stage and simple comb filter stage) and has a linear phase. This paper summarizes some key points of classical CIC filters and proposes a novel class of CIC FIR filter functions. A novel class of CIC filter functions maintains simplicity of FIR filters by avoiding the multipliers, but shows excellent performances in term of insertion loss in stopband and selectivity with respect to conventional CIC filters. A set of simulations along with illustrative examples is conducted in order to compare the attenuation characteristics of the classical CIC filter functions and the proposed novel class of selective CIC FIR filter functions. For the same level of a constant group delay τ=45.5s, a classical CIC filter function has insertion loss of 166.3dB, and designed novel filter function has a higher level of insertion loss 206.55dB.

SOPC-Based Multi-Rate Data Acquisition System

The paper uses soft nuclear CPU as controller created by SOPC, Combins with Ethernet controller components to realize the collection and transmission of multiple rate data.Discusses the characteristic parameterss affect to the CIC and hb filter, and has a optimal design: Demonstrates the best value range of CIC filters order number and extraction ratio, then compensates for bandpass characteristics; hb filter adopts multiphase structure which can improve efficiency.

Research and Design of Digital down Converter Based on Software Defined Radio

This paper makes a brief introduction on the current development trend of software radio and digital down converter status. The basic theoretical knowledge: Band-pass sampling theorem, digital signal orthogonal transformation theory, multi-rate signal processing theory. Based on these theories, use MATLAB complete the design and verification of mixing module, the extraction module (CIC filter, half-band filter and FIR filters), finally verify the correctness of the design, and implement DDC.

Design of five stage CIC decimation filter for signal processing applications

With the development of more compact and efficient ways of implementing digital logic on a silicon chip, most of the signal processing is being performed in the digital domain. The design of an efficient configurable digital decimation filter is focused in work. The Cascaded Integrator-Comb (CIC) filters are used as decimation filter. The five stage CIC filter is proposed in this paper. It does not require any multiplier circuit and also uses recursive or non-recursive filter[4]. CIC is the combination of equal number of Integrator and comb stages . The CIC filter is based upon a low-pass filtration system .These types of filter systems are utilized within the decimation that has the result upon decreasing the actual sample rate. The result of CIC filter impulse and magnitude response exposed using of MATLAB

Development of a new seismic-data acquisition station based on system-on-a-programmable-chip technology

<p>There has been considerable development of seismic detectors over the last 80 years. However, there is still a need to further develop new earthquake exploration and data acquisition systems with high precision. In particular, for China to keep up with the latest technology of these systems, it is important to be involved in the research and development, instead of importing systems that soon fall behind the latest technology. In this study, the features of system-on-a-programmable-chip (SoPC) technology are analyzed and used to design a new digital seismic-data acquisition station. The hardware circuit of the station was developed, and the analog board and the main control data-transmission board were designed according to the needs of digital seismic-data acquisition stations. High-definition analog-to-digital converter sequential digital filter technology of the station (cascade integrator comb filter, finite impulse response digital filter) were incorporated to provide advantages to the acquisition station, such as high definition, large dynamic scope, and low noise. A specific data-transmission protocol was designed for the station, which ensured a transmission speed of 16 Mbps along a 55-m wire with low power consumption. Synchronic acquisition was researched and developed, so as to achieve accuracy better than 200 ns. The key technologies were integrated into the SoPC of the main control data-transmission board, so as to ensure high-resolution acquisition of the station, while improving the accuracy of the synchronic acquisition and data-transmission speed, lowering the power consumption, and preparing for the follow-up efforts to tape out.</p>

Sinusoidal Signal Generator for ADC Testing in Mixed-Signal SOC

Sinusoidal signal can be used as stimulus to test static and dynamic parameters of ADC. A sigma-delta modulation based sinusoidal signal generator for ADC testing in SOC was introduced. The generator was built on the same chip with ADC. A numerical resonator generated a sinusoidal signal which was converted to a single bitstream by a sigma-delta modulator. Due to oversampling, the quantization noise was pushed to high frequency range. A high-quality sinusoidal signal was generated by low-pass filtering the bitstream. The sigma-delta modulator was inserted into the resonator to decrease silicon area overhead and calculate time. A cascaded integrator comb decimation filter was used as the low-pass filter. The amplitude and frequency of the output sinusoidal signal could be accuratly set by digital parameter of the generator to meet the requirement of static and dynamic performances testing. DOI: http://dx.doi.org/10.11591/telkomnika.v11i7.2818

Modified CIC 필터뱅크를 이용한 저전력 심장박동수 측정 알고리즘 및 구조

In this paper, low-power heart beat detection algorithm and structure is proposed. The proposed detection algorithm utilizes filter banks to display a specific beat per minute(BPM) from the heart beat signals. Since general filter banks need a lot of computation to calculate a BPM, we propose the filter banks structure using modified CIC(Cascaded Integrator Comb) filters. It is shown that the proposed modified CIC filter banks algorithm can display the BPM from the heart beat signals precisely and efficiently.

Performance Optimization of Digital Spectrum Analyzer With Gaussian Input Signal

Analog to digital converters (ADC) and cascade integrator-comb (CIC) filters are the basic modules in a digital intermediate frequency (IF) spectrum analyzer. The optimal output signal-to-noise ratio (SNR) of the digital IF spectrum analyzer with the Gaussian input signal is considered in this letter. The idea is to strike a trade-off between the saturation error and granular error when quantizing the Gaussian input signal. This letter firstly derives a relationship among the maximum allowed input signal amplitude, input signal power, ADC quantization bits and optimal quantization SNR. Besides, an optimal clipping strategy for the CIC decimation filter with variable decimation rates is proposed. Both numerical and simulation results are presented to demonstrate that the proposed clipping method is able to achieve significant SNR gain compared with the traditional rounding or truncation method.

Chebyshev Stopbands for CIC Decimation Filters and CIC-Implemented Array Tapers in 1D and 2D

The stopbands of a cascaded integrator-comb (CIC) decimation filter are ordinarily very narrow, as each results from a single multiple zero. Here response sharpening with a Chebyshev polynomial, using a previously reported CIC variant, separates each such multiple zero into an equiripple stopband. By trading unneeded depth at stopband center for improved depth at the stopband edge, the latter depth improves by some 6(N-1) dB in an Nth-order system. Increased computational complexity is modest: a few low-speed additions and multiplications by small integer coefficients that can often be chosen as powers of two. Alternatively, parameters can be configured to replace the many small stopbands with one large one, and this is demonstrated here with example spatial-processing CIC designs that create pencil beams for 1D and 2D receive antenna arrays.

저전력 기법을 사용한 고해상도 오디오용 Sigma Delta Decimation Filter 설계

Oversampling 기법을 사용한 analog-to-digital (A/D) 컨버터에서 샘플링 된 신호의 signal bandwidth를 낮추어 주기 위해 데시메이션 필터가 사용된다. 본 논문은 sigma-delta ADC에 사용될 수 있는 저전력 4 단 32 bit 데시메이터 필터 디자인을 제안한다. 디지털 데시메이션 필터는 CIC(cascaded integrator-comb) filter와 세 개의 half-band FIR filter로 이루어져 있다. 전력소모를 최소화하기 위하여 CIC filter에는 pipeline구조가 사용되었고, FIR 필터의 multiplier 구조를 최적화하기 위하여 Canonic Signed Digit (CSD) 코드가 사용되었다. 130nm CMOS 공정으로 설계 자동화 CAD 도구를 사용하여 타이밍, 면적, 전력소모를 최적화하여 98.304 ㎒ 주파수에서 697 ㎼의 전력을 소모면서 32 bit, 192 ㎑ 아웃풋을 낼 수 있다.

Design of Low Power Sigma Delta ADC

A Low power discrete time sigma delta ADC consisting of a second order sigma delta modulator and third order Cascaded Integrated Comb (CIC) filter is proposed. The second order modulator is designed to work at a signal band of 20K Hz at an oversampling ratio of 64 with a sampling frequency of 2.56 MHz. It achieves a signal to noise ratio of 85.2dB and a resolution of 14 bits. The CIC digital filter is designed to implement a decimation factor of 64, operating at a maximum sampling frequency of 2.56 MHz. A second order sigma delta modulator is implemented in 0.18micron CMOS technology using full custom design and the third order digital CIC decimation filter is implemented in verilog HDL. The complete Sigma Delta ADC, consisting of analog block of second order modulator and digital block of decimator consumes a total power 1.96mW.

Cascade linear phase recursive half-band filters implement the most efficient digital down converter

The digital down converter (DDC) is a fundamental component in modern DSP based receivers. The basic architecture is the DSP implementation of the Edwin Armstrong heterodyne circuit. It is formed by three processes, a quadrature heterodyne, a pair of low-pass filters, and an M-to-1 down sampler. The index M is the ratio of input to output bandwidth of the filtering process. When M is large, the filtering is often performed in two sub-filters: a cascade integrator comb (CIC) filter that performs most of the down sampling followed by a pair of half-band filters that perform spectral correction, some final bandwidth reduction, and the remainder of the down-sampling. The attraction of the CIC filter is that it performs the filtering without multiplies. In this paper we present two alternate filter structures that offer significant computational advantages over the conventional CIC based DDC. These architectures offer the minimum power implementation of a DDC and likely will find great value in battery operated radio receivers.

Digital Filter Design for CPT Atomic Clocks and FPGA Realization

We present our study result of applying digital filters in the Coherent Population Trapping (CPT) atomic clock. We design and realize the filter in a Field Programmable Gates Array (FPGA). The filter is constructed of a cascaded integrator-comb (CIC) decimation filter, a CIC compensation filter, and a finite-impulse response (FIR) filter in series. The CIC decimation filter operates for descending the sampling frequency and anti-aliasing, the CIC compensation filter refines the magnitude frequency response of the CIC decimation filter, and the FIR filter removes noises and extracts the wanted signal. By replacing the original analog filters with the digital filters in both laser frequency and microwave frequency servo loops, the experimental results show that the frequency stability of the CPT atomic clock is improved by 1×10τ (τ=1-100 s), the power dissipation is reduced by 23.6%, and the size of circuit board is also reduced.

On Passband and Stopband CIC Improvements Using a Second Order IIR Filter

This paper proposes an efficient second order IIR filter which considerably improves the passband as well as the stopband of the Cascaded-Integrator-Comb (CIC) filter. Using the polyphase decomposition of the proposed filte, all filtering can be moved to a lower rate, which is D times less than the high input rate, where D is the decimation factor. The overall phase response of the compensated CIC is approximately linear in the passband. The design parameters are the number of cascaded CIC filter N, the decimator factor D, the passband frequency w p , and a weighted parameter a.