NOVEL FPGA DESIGN AND IMPLEMENTATION OF DIGITAL UP CONVERTER

Abstract

In our world, communication systems play an importa nt role in day to day life. In wireless and wired c ommunication systems, signals are to be upsampled at the transmitter. Digital up converter (DUC) is a sample rate conversion techniq ue which is widely used to increase the sampling rate of an input signal. The digital up converter converts low sampled digital b aseband signal to a pass band signal. In this paper, we are going to design and i mplement a low noise digital up converter on a FPGA (Field Programmable Gate Array). In digital up converter, the input signal i s filtered and converted to higher sampling rate an d then it is modulated with the carrier signal generated from the direct digital sy nthesizer (DDS). This system consists of a cascaded integrator comb (CIC) interpolation filter, cascaded integrator comb comp ensation filter, multiplier and a direct digital synthesizer. The cascaded integrator comb interpolation filter performs upsampling of th e input signal and the cascaded integrator comb com pensation filter is used to compensate the losses of CIC filter by filtering th e input signal. The multiplier is used for multiply ing the upsampled signal from CIC filter with the carrier signal generated from DDS a nd gives the DUC output. In this DUC, the input si gnal is upsampled at the rate of eight. Here, two digital up converters are used and connected with an adder in order to obtain a low n oise output signal. The coding of this work is done in VHDL. The simulation and fu nctional verification is carried out using Xilinx I SE and FPGA implementation is carried out using Virtex 5.