Multistage Decimator Design for the Low-PHY PRACH Receiver

Abstract

This paper describes the design of a multistage decimator for the Physical Random Access Channel (PRACH) receiver based on the hybrid time/frequency domain architecture. Flexible structure of the multistage decimator allows to support all combinations of PRACH subcarrier spacings and carrier bandwidths defined in the 3rd Generation Partnership Project (3GPP) Release 15 for Frequency Range (FR) 1. Impulse responses of low pass filters for each decimation stage do not depend on a selected combination allowing to facilitate hardware implementation. The multistage decimator jointly uses the Cascaded Integrator-Comb (CIC) and Nyquist filters to minimize number of required multipliers. Acceptable degradation level due to decimation in the receiver performance is estimated based on requirements defined by the Radio Access Network (RAN) working group 4. Assuming no specific detection algorithm, it is shown that the proposed design introduces negligible degradation, less than 0.1 dB in the operating Signal-to-Noise Ratio (SNR) region.