Implementation of polyphase digital down converter for wireless applications

Abstract

This paper briefs the hardware-efficient polyphase digital down converter (DDC), which reduces the input sampling frequency to 3.64 GHz and produces a complex output to meet the IEEE 802.11ah wireless network standard. The design comprises a polyphase mixer (PM) filter and a lowpass polyphase finite impulse response (PFIR) filter. The PM filter uses a cascaded integrator comb (CIC) decimation filter based on multiplexer technology to potentially process parallel input interfaces and considerably reduce the sampling rate. The time-sharing mechanism of the CIC filter performs an efficient hardware implementation. Again, the improved design technique of the PFIR filter can effectively increase the operating speed and optimize power consumption. The proposed design offers high flexibility due to programmable sampling rate factors that can support multistandard communication systems. In addition, the design includes the truncation mechanism to protect against overflow errors and the fixed-point data type in each filter node to minimize the area requirements. The presented polyphase DDC is tested using the field-programmable gate array (FPGA) platform targeting the Xilinx Kintex-7 device. According to experimental results, the described DDC significantly reduces the logical resources and power dissipation associated with earlier design structures. The functional verification is tested to ensure the validation of the suggested design.