Canonic Signed Digit Research Articles

Higher order and optimized symmetric 2D FIR filter design and hardware architecture implementation using CSD-CSE

In this paper, an optimized and high-performance Two-Dimensional (2D) Finite Impulse Response (FIR) filter is designed and hardware architecture is implemented for image processing applications. The higher-order circular symmetric 2D FIR filter is designed using a modified McClellan Transformation called a P4 transformation. The perfect circular symmetry in the contour of the 2D FIR filter and less complexity and error are attained by this proposed P4 Transformation. Next, the designed filter coefficients are represented by the Canonical Signed Digit (CSD) number format to attain the multiplier-less design to avoid the power complexity multipliers. Further, to reduce the hardware complexity, the Common Subexpression Elimination (CSE) technique is utilized to reduce the number of adders and hence area and power are decreased. Each sub-filter corresponding to the CSD coefficient rows is realized and integrated as a 2D FIR filter using a Fully Direct-type architecture. This 2D FIR filter architecture is coded by Verilog and synthesized by Cadence tools in a 45 nm CMOS technology library. The Delay, Power Consumption (PC), and Area reports were generated by the Genus synthesis tool and compared with the state-of-the-art works. The PC, area, and delay of the proposed filter architecture are reduced to the minimum of 13.96%, 69.1%, and 1.4%, respectively when compared to the existing filter architectures. The maximum of 10.48 times and a minimum of 1.18 times of Area Delay Product (ADP), and a maximum of 10.69 times and a minimum of 1.063 times of Power Delay Product (PDP) are smaller than the existing 2D filter architectures.

A Σ-Δ ADC with a DPOQ system and a new multi-Stage digital filter

This paper proposes a high-precision Sigma Delta ADC for automotive electronic sensors and delves into methods for optimizing quantizers and filters, with a focus on DPOQ quantizers and hybrid CIC filters. This ADC features a Dual-path One-bit Quantization (DPOQ) System, which improves the accuracy of Sigma-Delta ADCs while reducing hardware consumption. Meanwhile, this paper presents a new multistage digital filter. The filter uses a cascade of multiple filters, including cosine-like (CL), cascaded integral comb (CIC), interpolated second-order polynomial (ISOP), and half-band (HB) filters, to enhance the ADC’s accuracy. The filter are designed using canonical signed digit (CSD) and common subexpression (CSE) optimized the design algorithm of the filter, to reduce hardware resource consumption and improve computational performance. The ADC is synthesized using 180 nm CMOS technology, achieving an output SNDR of 96.26 dB, ENOB of 15.73 bits, and total power of 518.35 uW.

Multiplier-less Broadband and Linear Phase Digital Hilbert Transformers

The Hilbert transformation for generating the analytic signal or signal envelope is widely used in modern communication receivers, in radar and sonar systems. It introduces a 90∘\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$90^{\\circ }$$\\end{document} phase shift of the input signal. Since the impulse response of the ideal Hilbert transformer is non-causal, it must be approximated by an FIR or IIR filter. This paper shows results of novel algorithms for designing broadband digital IIR Hilbert transformers and its implementation. The designs employ Galerkin or collocation techniques. The transfer function of the Hilbert transformer is a rational polynomial of low order and exhibits approximately linear phase. The filters match the 90∘\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$90^{\\circ }$$\\end{document} phase shift requirement of Hilbert transformers almost perfectly and exhibit approximately constant group delay in the passband. The achieved image rejection ratio is typically larger than 50 dB. The quantization of the filter coefficients is realized by a Canonical Signed Digit (CSD) representation, reducing the hardware resources compared with two’s complement. The resulting filters are multiplier-less, which is crucial for high-speed signal processing and low power consumption. The design techniques and the CSD representation are realized in a MATLAB toolbox. The filters were moreover implemented in VHDL and SystemC. Additionally, a MATLAB tool for automatically generating a VHDL package containing the filter parameters has been implemented.

ExTern: Boosting RISC-V core performance using ternary encoding

This paper presents an effective μ-architectural design method, called ExTern, to enhance the performance of a RISC-V processor experiencing computation bottlenecks. ExTern involves integrating Canonical Signed Digit (CSD) representation, a ternary number system enabling carry/borrow-free addition/subtraction in constant time O(1), into the RISC-V processor, particularly into the execution stage. Furthermore, it adopts an extended six-stage pipeline architecture to maximize employed encoding benefits, leading to more improvement in overall execution time and throughput. Despite the presence of optimized circuits, such as fast carry chain (CARRY4) modules for binary encoding on FPGA, the customized processor applying ExTern, RISC-VT, showcases remarkable improvement in computation performance. Experimental results demonstrate a 34.3% (12.2%) improvement in working frequency leading to a lower 31% (11.5%) execution time and a 32% (12%) increase in throughput compared to a State-of-the-Art open-source five(six)-stage RISC-V processor.

A Multiplier-Less FRM-Based Reconfigurable Regulated Bank of Filter for Spectrum Hole Detection in IoT

A promising solution for the detection of spectrum holes in the Internet of Things networks is the cognitive radio (CR) system, which is used to identify spectrum holes effectively. The intention of this work is to design a low-complexity Reconfigurable Regulated Bank of Filter (RRBF) structure for spectrum hole detection in IoT networks. The RRBF structure is designed by utilizing the Frequency Response Masking (FRM) approach and the Cosine Modulation Technique (CMT). Using the RRBF structure, multiple sharp non-uniform channels are generated for efficient spectrum hole detection in IoT networks. With the aid of an example, the performance and computational complexity of the RRBF structure are demonstrated. The result shows that the RRBF structure has a fewer multipliers than other existing methods. To obtain hardware-efficient realization, the RRBF structure is made of multiplier-less by incorporating Canonical Signed Digit (CSD), Multi-Objective Artificial Bee Colony (MOABC), and Shift Inclusive Differential Coefficients (SIDC) with Common Sub-expression Elimination (CSE) optimization techniques.

An efficient high performance reconfigurable canonical sign digit architecture for software defined radio

Software defined radios (SDRs) are highly motivated for wireless device modelling due to their flexibility and scalability over alternative wireless design options. The evolutionary structure of finite impulse response (FIR) filters was designed for a proposed reconfigurable canonical sign digit (CSD) approach. Considering the complex trade-off, this is accomplished with many FIR taps, which is a challenging assignment. On the baseband processing side, design is given with parameterization-controlled FIR filter tap selection. Optimal processing models to overcome the reconfigurable design issues associated with the SDR system for a multi-standard wireless communication system root cosine filter standard are often used to implement multiple FIR channelization topologies, each of which is tied to a particular in-phase and quadrature (IQ) symbol. Additionally, it demonstrates the viability of using a multi-modulation baseband modulator in the SDR system for next-generation wireless communication systems to maximise adaptability with the least amount of computational complexity overhead. The proposed multiplier-less FIR filter-based reconfigurable baseband modulator, according to the experimental results, offers a 6% complexity reduction and a 47% improvement in performance efficiency over the current SDR system.

Design of CSD based bi-orthogonal wavelet filter bank for medical image retrieval

Two-channel wavelet filter-banks (FBs) are universally used in many applications of signal processing. In this work, design of a bi-orthogonal wavelet FB with low complexity is suggested. The proposed design is based on canonical signed digit (CSD) implementation of the bi-orthogonal wavelet FB. CSD technique has been applied to the FB to eliminate the power consuming multipliers and to reduce the number of shifters and adders in the implementation of bi-orthogonal FB. The suggested FB design is suitable for the application of high speed signal processing applications. In addition, the proposed bi-orthogonal wavelet FB is implemented on hardware using Field Programmable Gate Array (FPGA) board Kintex-7 from Xilinx. It is found that the suggested bi-orthogonal wavelet FB attained low digital hardware requirement as compared to well-known rationalized existing bi-orthogonal wavelet FBs. The efficacy of the suggested wavelet FB is demonstrated on medical image retrieval application. NEMA, OASIS, and EXACT09, three publicly accessible medical image datasets, are utilized to measure the efficacy of image retrieval. It is shown that the suggested bi-orthogonal wavelet FB performs better than the bi-orthogonal wavelet FBs existing that are being used.

Near-optimal Multiplier-Less Broadband Noise Shaping Filters

Noise shaping (NS) filters reduce the quantization noise power in one or more frequency band(s) while amplifying it in other bands. Narrow-band noise shaping filters are state of the art in audio signal processing, analog-digital and digital-analog conversion, direct digital synthesis, and other applications. However, it is much more difficult to design broadband NS filters. Since NS filters are used in feedback branches, they must therefore be designed direct path free which imposes a constraint on the filter coefficients. This constraint leads to prohibitive large filter coefficients employing state of the art filter design techniques.This paper investigates the theoretical bound for NS filters and shows results about a novel design method for broadband FIR and IIR noise shaping filters and its multiplier-less hardware implementation. The method employed is a purely numerical approximation technique and leads to filter designs close to the discussed theoretical bound. The quantization of the filter coefficients is performed by a Canonical Signed Digit (CSD) representation of the coefficients. Two alternative architectures for the implementation of the filters are discussed. The design technique and the CSD quantization are realized in a MATLAB toolbox. The filters were moreover implemented in VHDL.

Design of canonical signed digit multiplier using spurious power suppression technique adder

Reducing power consumption is a major challenge in developing integrated processors for smart portable devices. This is particularly important for extending battery life and ensuring extended usage of the device. However, some DSP processing applications involve complex algorithms that consume more power, which poses a significant challenge in designing DSP applications for VLSI circuits. To address this issue, low-power consumption methodologies are required. Although various strategies have been developed to reduce power consumption, they have not demonstrated a significant decrease in dynamic power consumption, which is the primary factor determining the total amount of power dissipation.The focus of this research is to develop a low-power multiplier using the spurious power suppression technique (SPST), a method that divides the arithmetic unit into the most significant part (MSP) and least significant part (LSP) and turns off the MSP when it is not required for computation. This approach reduces dynamic power and overall power consumption of the VLSI combinational circuit. The proposed system also utilizes canonical signed digit (CSD) representation to further reduce power usage.The system was designed using Cadence design suite, and the results showed a significant reduction of 35.8% in power consumption for a 32-bit SPST-enabled CSD multiplier. The proposed system’s total power consumption is 0.561 mW. Additionally, the proposed system was used in a power and area-efficient 256-point FFT architecture, resulting in an 86.6% reduction in power consumption. This system is suitable for real-time applications such as systems that use orthogonal frequency division multiplexing.

Design and Implementation of High Speed Low Power Decimation Filter for Hearing AID Applications

This work is focused on designing and implementing a decimation filter specifically intended for use in hearing aid applications. The filter utilizes distributed arithmetic (DA) and is described in this brief. Our proposal involves the development of a reconfigurable finite impulse response (FIR) filter, which utilizes both offset binary code (OBC) and binary distributed arithmetic (DA) techniques. Additionally, we utilize canonic signed digit (CSD) representation to develop decimation filters, which include the CIC filter, half band filter, and corrector filter. In this work, we have implemented a decimation filter using Matlab Simulink. We have utilized Xilinx Vivado 19.2 to execute the FIR filters, binary DA filters, and OBC DA-based filters. Our focus is on implementing these filters using VLSI architecture, in order to achieve low power consumption, reduced latency, less area, and fast speed.

A Low-Complexity Multiplier-Less Filter Bank Based on Modified IFIR for the SDR Channelizer

Digital filter banks are extensively used in an SDR channelizer for channelization. The objective of this research work is to design a low computational complexity FIR filter bank for generating sharp transition width channels for SDR. The design of unified and variable bandwidth channels for SDR using the proposed structure is based on the modified IFIR filter structure and cosine modulation technique (CMT). The performance of the proposed structure is demonstrated with the help of an example. The results show that the multiplier complexity of the proposed structure is less than those of other state-of-the art methods. The optimization techniques are incorporated in this work to further reduce the complexity of the proposed structure. With the help of canonical signed digit (CSD), multi-objective artificial bee colony (MOABC) and shift inclusive differential coefficients (SIDC) – common sub-expression elimination (CSE) optimization, the filter used in this structure is made multiplier-less.

Fully Digital Calibration Technique for Channel Mismatch of TIADC at Any Frequency

This paper presents a fully digital modulation calibration technique for channel mismatch of TIADC at any frequency. By pre-inputting a test signal in TIADC, the mismatch errors are estimated and stored, and the stored values will be extracted for compensation when the input signal is at special frequency which can be detected by a threshold judgement module, thus solving the problem that the traditional modulation calibration algorithm cannot calibrate the signal at special frequency. Then, by adjusting the operation order among the error estimation coefficient, modulation function and input signal in the calibration loop, further, the order of correlation and modulation in the error estimation module, the complexity of the proposed calibration algorithm is greatly reduced and it will not increase with the number of channels of TIADC. What's more, the hardware consumption of filters in calibration algorithm is greatly reduced by introducing a CSD (Canonical Signed Digit) coding technique based on Horner's rule and sub-expression sharing. Applied to a four-channel 14bit 560MHz TIADC system, with input signal at 75.6MHz, the FPGA verification results show that, after calibration, the spurious-free dynamic range (SFDR) improves from 33.47dB to 99.81dB and signal-to-noise distortion ratio (SNDR) increases from 30.15dB to 81.89dB.

A Sub-GHz multimode digital polar transmitter for 802.11ah and NB-IoT applications

This paper presents a sub-GHz multimode efficiency-enhanced digital polar transmitter for IoT applications. The Class-G technique and wideband matching network are introduced in the switched-capacitor digital power amplifier (DPA) to enhance the 6 dB back-off efficiency and achieve 550–950 MHz wide frequency coverage. The digital baseband processing module is flexibly reconfigurable to support both 802.11ah and NB-IoT protocols. Moreover, the canonic signed digit (CSD) coding and first-order hold (FOH) interpolation techniques are employed to reduce power consumption. Implemented in 55 nm CMOS technology, this digital transmitter (DTX) achieves 23.7dBm peak power, 44.6% peak PAE and 36.1% PAE at 6 dB power back-off at 800 MHz. The DTX obtains 16.7dBm average output power, 33.9% average PAE with −28.8 dB EVM for the 2 MHz 64QAM 802.11ah signal, and 18.6dBm average output power, 37.5% average PAE with −19.8 dB EVM for the 12-subcarrier 180 kHz NB-IoT signal.

Design and Implementation of Sigma-Delta ADC Filter

This paper presents a digital decimation filter based on a third-order four-bit Sigma-Delta modulator. The digital decimation filter is an important part of the Sigma-Delta ADC and is designed to make the Sigma-Delta ADC (Analog-to-Digital Converter) meets the requirements of Signal-to-Noise Ratio (SNR) not less than 120 dB and Equivalent Number of Bits (ENOB) not less than 20 bits. It adopts a three-stages cascaded structure including a Cascaded Integrator Comb (CIC) decimation filter, a Finite Impulse Response (FIR) compensation filter, and a half-band (HB) filter. This structure effectively reduces about 13% multiplier cells and memory cells. The coefficient symmetry technique and CSD (Canonic Signed Digit) coding technique are used to optimize the parameters of the filter, which further reduces the computational complexity. After optimization, the circuit area is reduced by about 15%, and the logic resources are decreased by about 23%. The Verilog hardware description language is used to describe the behavior of the digital decimation filter, and the simulation is carried out based on the VCS (Verilog Compile Simulator) platform. At the same time, the prototype verification is implemented on the Xilinx Artix-7 series FPGA, and the ADC achieves 113 dB SNR and 18.5 bits ENOB. Finally, the Sigma-Delta ADC is fabricated on SMIC 0.18 μm CMOS process with the layout area of 714.8 μm × 628.4 μm and the power consumption of 11.2 mW. The more tests for the fabricated prototypes will be performed in the future to verify that the Sigma-Delta ADC complies with the design specifications.

VLSI architecture design and implementation of 5/3 and 9/7 lifting Discrete Wavelet Transform

Discrete Wavelet Transform (DWT) is considered among the few computationally expensive block of multimedia compression standards. In this work, we proposed a reduced hardware complexity VLSI architectures of 5/3 and 9/7 lifting bi-orthogonal DWT for multimedia applications. The architecture uses a combination of Distribute Arithmetic (DA) and Canonical Signed Digit (CSD) based implementation to reduce the hardware complexity. The resulting lifting based architecture discretely finds optimized number of sum of products to give minimum realization. The architecture is implemented on Field Programmable Gate Array (FPGA) with results compared with known classical and other optimized DWT architectures.

Design and Performance Analysis of Improved FIR Filter using Ultra-Scale FPGA

It is discussed in many studies and demonstrated in many pieces of research that based on certain applications, analog design of filter has several issues including complex design, re-use limitations, and accuracy of generating the output at various frequencies. Therefore, instead of analog filter design, the digital design of the filter is preferred for both Finite and Infinite Impulse Response Filter. This paper demonstrates the design of the digital Finite Impulse Response (FIR) filter designed is demonstrated using Ultra-Scale Field Programming Gate Array (FPGA) having chip XCKU3P. The filter is designed using a coefficient multiplier via Canonic Signed Digit (CSD) Technique. The optimized design of the digital filter is conducted via real-time implementation is performed using Ultra-Scale FPGA. The filter is designed and evaluated with an ordinary filter at 10 MHz and 10 GHz frequencies. The performance analysis of the system is illustrated using the response rate at the bitstream of 16-bit. In the results, it is demonstrated that for 10 MHz frequency design FIR filter in FPGA the 30% faster response filter is achieved at for 10 GHz, the 15% faster response is achieved at the I/O standard of Low Voltage Complementary Metal Oxide Semiconductor (LVCOMS). The optimization of 30% in terms of the response time of the filter is attained using the proposed work. The proposed improved FIR filter design using Ultra-Scale FPGA helps in increasing design performance to increase the speed of overall response of FIR filter that is lacking in ordinary Filters.

A 65nm/0.448 mW EEG processor with parallel architecture SVM and lifting wavelet transform for high-performance and low-power epilepsy detection

In recent years, low-power and wearable biomedical testing devices have emerged as a key answer to the challenges associated with epilepsy disorders, which are prone to crises and require prolonged monitoring. The feature vector of the electroencephalographic (EEG) signal was extracted using the lifting wavelet transform algorithm, and the hardware of the lifting wavelet transform module was optimized using the canonic signed digit (CSD) coding method. A low-power EEG feature extraction circuit with a power consumption of 0.42 mW was constructed. This article employs the support vector machine (SVM) technique after feature extraction to categorize and identify epilepsy. A parallel SVM processing unit was constructed to accelerate classification and identification, and then a high-speed, low-power EEG epilepsy detection processor was implemented. The processor design was completed using TSMC 65 nm technology. The chip size is 0.98 mm2, operating voltage is 1 V, operating frequency is 1 MHz, epilepsy detection latency is 0.91 s, power consumption is 0.448 mW, and energy efficiency of a single classification is 2.23 μJ/class. The CHB-MIT database test results show that this processor has a sensitivity of 91.86% and a false detection rate of 0.17/h. Compared to other processors, this processor is more suitable for portable/wearable devices.

Effective Hardware Accelerator for 2D DCT/IDCT Using Improved Loeffler Architecture

This paper proposes an effective hardware accelerator for 2D <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$8\times 8$ </tex-math></inline-formula> discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) using an improved Loeffler architecture. The accelerator optimizes the data stream of the Loeffler 8-point 1D DCT/IDCT according to the characteristics of image and video processing. An 8-stage pipeline structure greatly improves the processing speed by reasonably dividing the number of clock cycles and simplifying the arithmetic operations in each cycle. The multiplication-free approximation of the DCT coefficients is implemented through adders and shifters, combined with both fixed-point and canonic signed digit (CSD) coding. In particular, the proposed fast parallel transposed matrix architecture achieves the function of row-column coefficient conversion with lower circuit complexity. The FPGA implementation of the proposed architecture uses a Virtex-7 XC7VX330T device, running at 288 MHz with a throughput of 558 M Pixel/sec, and a Full HD real-time frame rate of up to 269 fps. Only 33 cycles are required to complete the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$8\times 8$ </tex-math></inline-formula> blocks of 2D DCT/IDCT, which can be used as a high-performance hardware accelerator for image and video compression encoding.

An Efficient FIR Filter Based on Hardware Sharing Architecture Using CSD Coefficient Grouping for Wireless Application

FIR filter is an essential part of digital signal processing that is extensively used in many areas such as wireless applications and digital processing system. The FIR filter design is inherently stable and has a linear phase characteristic under symmetric conditions, but its implementation often involves complexity and a large filter length to achieve specific design requirements. In this paper, the complexity of the FIR filter is reduced by eliminating the repeated subexpression in a canonic signed digit (CSD) number system based filter operation. A new grouping method has been proposed for the CSD number system-based filter coefficient to minimize the number of unpaired nonzero bits in the filter coefficient. The statistical analysis of the proposed grouping method is performed and compared with other existing schemes. The number of unpaired nonzero bits in the proposed grouping scheme is reduced by an average of 24.11\(\%\) as compared to other existing schemes. Further, an efficient FIR filter with hardware sharing architecture is designed and implemented to achieve a 14.65\(\%\) reduction in average power consumption, and the average operation speed is increased by 10.1\(\%\) compared to the other existing filter structures.

Design and Development of Diminution of Multiplier in FIR Sieve Consuming Mutual Sub-Expression Removal Algorithm

The difficulty of Finite-Impulse-Response (FIR) sieve out is ruled with means of that wide variety of adders or subtractors that are consumed toward enforce these co-green multipliers. The Common-Sub-expression-Elimination (CSE) set of rules is founded totally at that Canonical-Signed-Digit (CSD) depiction of clear out co-efficient pro imposing stumpy difficulty FIR sieves. Now, decrease of multiplier inside rectilinear phase FIR sieves is completed through changing this multiplier quantity toward Minimum-Signed-Powers-of-Two (MNSPT) or Canonical-Signed-Digit (CSD) illustration of this multiplier respectively. This multiplier may be executed consuming a sequence of changes and accompaniments or deductions. This CSE algorithm is expended toward discover and dispose of additional commonplace sub-expressions amongst sieve coefficients whichever ends up inside energy and vicinity convertible at the same time as executed inside FIR sieves. This Common-Sub-expression-Elimination (CSE) approach toward be consumed pro this VLSI layout will outcome in condensed multiplier inside Finite-Impulse-Response (FIR) clear out by a trivial quantity of adders and records.