Canonic Signed Digit Research Articles

FPGA Based Equiripple Canonical Signed Digit FIR Filter for Audio Applications

Objective: In this work, the selection of equiripple optimum design approach along with Canonical Signed Digital (CSD) representation of filter coefficients give an efficient and simplified design for Finite Impulse Response (FIR) digital filter. Methods/Statistical Analysis: The modern sophisticated communication devices demand for digital filters having the best possible performance. In this paper the author introduces design of FPGA based CSD finite impulse response filter with the help of an equiripple design method which provides the best possible frequency response. The direct form structure adopted in realizing this filter has better performance in terms of cost, power consumption and speed of operation. Findings: The CSD representation of filter coefficients reduces the complexity of multipliers. The resource utilization of designed FIR CSD filter analyzes with the help of a number of performance parameters and compares with FIR fully parallel filter. The proposed filter uses MATLAB fdatool to determine filter coefficients and Xilinx ISE 9.2i to simulate the performance of filter. Applications: The proposed filter can be used in several audio applications.

Reconfigurable Low Pass FIR Filter Design using Canonic Signed Digit for Audio Applications

Objectives: This paper highlights the design of multiplier-less FIR filter. The binary coefficients are replaced by Canonic Signed Digit representation which reduces the complexity of the design. Methods/Statistical Analysis: In the current scenario more research is going on the optimization of Finite Impulse Response filters with less complex hardware design. The FIR filters performance depends on number of coefficient multipliers. The multipliers are expensive in terms delay area and power. In the CSD based filter, the number of non-zero bits is reduced. This proposed filter is designed in MATLAB, simulated in ISE environment and implemented on FPGA. Findings: The proposed filter is implemented on three FPGA devices, Xilinx's Spartan-3E, xc3s500e-4fg320, Virtex 2P, 2vp30ff1152-5 and Virtex 5P xc5v1x50t-3ff1136. Improvements: The designed structure uses reduced number of hardware components like slices, look up tables (LUTs) and flip-flops as compared to different structures and offers better performance.

High-throughput Low-complexity Mixed-radix FFT Processor using a Dual-path Shared Complex Constant Multiplier

This paper presents a high-throughput lowcomplexity 512-point eight-parallel mixed-radix multipath delay feedback (MDF) fast Fourier transform (FFT) processor architecture for orthogonal frequency division multiplexing (OFDM) applications. To decrease the number of twiddle factor (TF) multiplications, a mixed-radix 2 4 /2 3 FFT algorithm is adopted. Moreover, a dual-path shared canonical signed digit (CSD) complex constant multiplier using a multi-layer scheme is proposed for reducing the hardware complexity of the TF multiplication. The proposed FFT processor is implemented using TSMC 90-nm CMOS technology. The synthesis results demonstrate that the proposed FFT processor can lead to a 16% reduction in hardware complexity and higher throughput compared to conventional architectures.

H‐RADIX a new heuristic for a single constant multiplication

In the authors’ previous work on the multiplication by a constant, optimisations have been done on the RADIX-2 r heuristic based on Radix-2 r arithmetic, which is a fully predictable, and a sub-linear-runtime heuristic. This improved version of RADIX-2 r is called RADIX-2 r +. The latter makes the former more competitive in term of average number of additions compared with existing heuristics. In this study, the authors propose a new heuristic for multiplication by a constant, denoted H-RADIX, which combines RADIX-2 r + with a common sub-pattern (Lefevre's CSP) heuristic. It belongs to the category of common subexpression elimination algorithm. Results of the designed hybrid algorithm (H-RADIX), namely, the average number of additions and the smallest value that requires q adders, are compared with the standard canonical signed digit (CSD) representation, RADIX-2 r +, and Lefevre's CSP algorithms. The results highlight the efficiency of the designed heuristic, up to N-bits = 64. H-RADIX uses 37.496, 5.015 and 3.082% less additions than CSD, RADIX-2 r +, and Lefevre's CSP, respectively.

A novel design and implementation technique for low complexity variable digital filters using multi-objective artificial bee colony optimization and a minimal spanning tree approach

Farrow structure in canonic signed digit (CSD) space is an efficient approach for the design of real-time tunable finite precision variable digital filters (VDFs). A novel design method for Farrow structure based VDFs in CSD space with reduced hardware complexity is proposed in this paper. The design approach makes use of the multi-objective artificial bee colony (MOABC) optimization algorithm with an integer search space to find the optimal Farrow sub-filter coefficients. Further, a novel low complexity implementation approach for the finite precision VDF using a minimal spanning tree approach is also proposed. The minimal spanning tree approach deploys the shift inclusive differential coefficients (SIDCs) and the different shifted SIDCs with common sub-expression elimination (CSE) to optimize the multiple constant multiplications involved in the filter realization. The attractive feature of our proposed method using MOABC and SIDCs with CSE lies in the increased hardware complexity reduction of the VDFs, compared to the existing methods, which in turn reduces the hardware resource utilization and power consumption drastically compared to the continuous coefficient VDFs. The hardware implementation of the VDF using the proposed method has also been done using Xilinx ISE to analyse the reduction in the hardware complexity and dynamic power.

Design of multiplierless prototype filter for two‐channel filter bank using hybrid method in FCSD space

In this work, a hybrid method-based design of multiplierless two-channel filter bank has been proposed with a given stopband attenuation (As) and roll-off factor. Windowing method has been used for efficient design of a prototype filter with novelty of exploiting quantised coefficients in canonical sign digit (CSD) and factorised canonical sign digit (FCSD) space by merging the concept of particle swarm optimisation and artificial bee colony algorithm. The quantised filter coefficients are optimised by varying cut-off frequency such that the magnitude response of prototype filter is approximately reduced to 0.707 at quadrature frequency. The implemented filter is synthesised using target field programmable gate arrays XC3S500E-4-FG320 on Xilinx Spartan 3E starter board. The performances of designed prototype filter is compared with the earlier published works in terms of reconstruction error, amplitude distortion, slices, flip-flops, four-input lookup tables and adders. The synthesis results demonstrate that the significant reduction in hardware is achieved in term of adder gain. For filter order, N = 32, and word length 12, the adder gain achieved in CSD and FCSD is 41.77 and 43.07%, respectively, while for N = 30, it is 35.44% in CSD and 36.70% in FCSD, respectively.

Efficient digit serial architecture for sign based least mean square adaptive filter for denoising of artefacts in ECG signals

Variants of Least Mean Square algorithm, namely the Sign Error, Sign Regressor and Sign-Sign Least Mean Square algorithms are meant for reducing computational complexity in digital adaptive filters in denoising electrocardiogram signals. In adaptive filtering using Sign-Sign algorithm, the adders and multipliers in the existing method take the coefficients in canonic signed power of two form which assures that between two non-zero there should be one zero in signed power of two digits and they can process only one bit per clock cycle and so is the filter resulting in low speed. In this paper, digit serial adder and digit serial multiplier are proposed to design the Sign-Sign Least Mean Square filter, which increases the speed by processing two bits per clock cycle. The digit serial adder and digit serial multiplier are used to design the Sign-Sign based adaptive filter in which unfolding technique is used for digit serial realisation. The unfolding factor of K = 2 is chosen to increase the speed of the design. The coefficients and its inputs are represented in Canonic Signed Digit form. Adder, multiplier, adaptive filter of both existing and proposed method are simulated using Mentor Graphics and synthesised using Synopsys Design Compiler Tool with 90 nm technology. From the results it is observed that the speed of the proposed digit serial Sign-Sign Least Mean Square filter is increased by 54.5% and the area of the filter is decreased by 4.21% compared to the bit serial Sign-Sign Least Mean Square filter.

Efficient digit serial architecture for sign based least mean square adaptive filter for denoising of artefacts in ECG signals

Variants of Least Mean Square algorithm, namely the Sign Error, Sign Regressor and Sign-Sign Least Mean Square algorithms are meant for reducing computational complexity in digital adaptive filters in denoising electrocardiogram signals. In adaptive filtering using Sign-Sign algorithm, the adders and multipliers in the existing method take the coefficients in canonic signed power of two form which assures that between two non-zero there should be one zero in signed power of two digits and they can process only one bit per clock cycle and so is the filter resulting in low speed. In this paper, digit serial adder and digit serial multiplier are proposed to design the Sign-Sign Least Mean Square filter, which increases the speed by processing two bits per clock cycle. The digit serial adder and digit serial multiplier are used to design the Sign-Sign based adaptive filter in which unfolding technique is used for digit serial realisation. The unfolding factor of K = 2 is chosen to increase the speed of the design. The coefficients and its inputs are represented in Canonic Signed Digit form. Adder, multiplier, adaptive filter of both existing and proposed method are simulated using Mentor Graphics and synthesised using Synopsys Design Compiler Tool with 90 nm technology. From the results it is observed that the speed of the proposed digit serial Sign-Sign Least Mean Square filter is increased by 54.5% and the area of the filter is decreased by 4.21% compared to the bit serial Sign-Sign Least Mean Square filter.

FPGA based Band Pass FIR Filter using Factored Canonic Signed Digit Technique for Satellite Application

FPGA based Band Pass FIR Filter using Factored Canonic Signed Digit Technique for Satellite Application

An area-efficient and low-power 64-point pipeline Fast Fourier Transform for OFDM applications

In an orthogonal frequency division multiplexing (OFDM) based wireless systems, Fast Fourier Transform (FFT) is a critical block as it occupies large area and consumes more power. In this paper, we present an area-efficient and low power 16-bit word-width 64-point radix-22 and radix-23 pipelined FFT architectures for an OFDM-based IEEE 802.11a wireless LAN baseband. The designs are derived from radix-2k algorithm and adopt a Single-Path Delay Feedback (SDF) architecture for hardware implementation. To eliminate the complex multipliers and read-only memory (ROM) which is used for internal storage of twiddle factor coefficients, the proposed 64-point FFT employs a Canonical Signed Digit (CSD) complex constant multiplier using adders, multiplexers and shifters. The complex constant multiplier (CCM) is modified using common sub-expression sharing block that reduces the area of the design. The proposed radix-22 and radix-23 pipelined FFT architectures are modeled and implemented using TSMC 180nm CMOS technology with a supply voltage of 1.8V. The implementation results show that the proposed architectures significantly reduces the hardware cost and power consumption in comparison to existing 64-point FFT architectures.

높은 비가청성을 갖는 믹스 음악의 크기 변조 오디오 워터마킹 기술에 관한 연구

In this paper, we propose a watermarking technology for a mixed music. The mixed music means recreated music that contained a number of musics in one audio clip. Royalty associated with the audio content is typically imposed by the full audio content. However, the calculation of royalties gives rise to conflict between copyright holders and users in the mixed music because it uses not full audio content but a fraction of that. To solve the conflict related with the mixed music, we propose a audio watermarking technique that inserts different watermarks for each audio in the audio that make up the mixed music. The proposed watermarking scheme might have poor SNR (signal to noise ratio) to embed to each audio clip. To overcome poor SNR problem, we used inaudible pseudo random sequence which modifies typical pseudo random sequence to canonical signed digit (CSD) form. The proposed method verifies the performance by each watermark extraction and the time internal estimation valies from the mixed music.

Design of efficient circularly symmetric two-dimensional variable digital FIR filters

Circularly symmetric two-dimensional (2D) finite impulse response (FIR) filters find extensive use in image and medical applications, especially for isotropic filtering. Moreover, the design and implementation of 2D digital filters with variable fractional delay and variable magnitude responses without redesigning the filter has become a crucial topic of interest due to its significance in low-cost applications. Recently the design using fixed word length coefficients has gained importance due to the replacement of multipliers by shifters and adders, which reduces the hardware complexity. Among the various approaches to 2D design, transforming a one-dimensional (1D) filter to 2D by transformation, is reported to be an efficient technique. In this paper, 1D variable digital filters (VDFs) with tunable cut-off frequencies are designed using Farrow structure based interpolation approach, and the sub-filter coefficients in the Farrow structure are made multiplier-less using canonic signed digit (CSD) representation. The resulting performance degradation in the filters is overcome by using artificial bee colony (ABC) optimization. Finally, the optimized 1D VDFs are mapped to 2D using generalized McClellan transformation resulting in low complexity, circularly symmetric 2D VDFs with real-time tunability.

一种低面积低功耗RGB到YCbCr色彩空间转换电路实现方法

本文提出了一种低面积低功耗RGB与YCbCr色彩空间转换的电路实现方法。首先提出一种结合简化加法器图(Reduced Adder Graph, RAG)的公共子表达式消除(Common Subexpression Elimination, CSE)的电路实现，然后提出一个提高精度的补偿方法。最后采用TSMC 0.18um工艺对所提出的算法进行综合和布局布线。仿真和综合结果表明相比于传统的正则有符号数字(Canonic Signed Digit, CSD)编码系统，采用本文提出的结合CSE和RAG的RGB到YCbCr空间转换电路实现方法面积和功耗减小了20%，补偿算法提高了系统精度。 This paper presents a low-area and low-power circuit implementation of high-precision color space conversion from RGB to YCbCr. Firstly, an efficient circuit implementation combining com-mon-subexpression-elimination (CSE) with reduced-adder-graph (RAG) is presented. Secondly, a compensation method is proposed to enhance the precision. Finally, the synthesized results of a TSMC 0.18 um standard cell library are given. By using the proposed circuit implementation of color space conversion from RGB to YCbCr combining CSE and RAG without compensation, the results show that the area and power are reduced by about 20% than the traditional Canonic Signed Digital (CSD) method. With the compensation algorithm, the precision is much higher.

An Effective Allocation of Non-Zero Digits for CSD Coefficient FIR Filters Using 0-1PSO

In this paper, a novel method for effective allocation of non-zero digits in design of CSD (Canonic Signed Digit) coefficient FIR (Finite Impulse Response) filters is proposed. The design problem can be formulated as a mixed integer linear programming problem, which is well-known as a NP-hard problem. Recently, a heuristic approach using the PSO (Particle Swarm Optimization) for solving the problem has been proposed, in which the maximum number of non-zero digits is limited in each coefficient. On the other hand, the maximum number of non-zero digits is limited in total in the proposed method and the 0-1PSO is applied. It enables an effective allocation of nonzero digits and provides a good design. Several examples are shown to present an efficiency of the proposed method.

Design of FRM-based MDFT filter banks in the canonic signed digit space using modified meta-heuristic algorithms

An optimal totally multiplier-less sharp transition width Modified Discrete Fourier Transform (MDFT) filter bank is proposed in this work. Since, here, the aim is to design a low complexity sharp transition width MDFT filter bank, the filters of the filter bank are designed using Frequency Response Masking technique to reduce the number of multipliers and hence the complexity. To replace multipliers with adders and shifters, the filter coefficients are converted into the Canonic Signed Digit space. In order to reduce the number of adders and shifters in the multiplier-less implementation, restricted number of non-zero bits is used in the conversion. This may degrade the performances of the MDFT filter bank. The performances are improved using modified meta-heuristic algorithms. A new hybrid algorithm which combines the qualities of Harmony Search Algorithm and Gravitational Search Algorithm is proposed in this work to optimise the performance of the MDFT filter bank.

Meta-heuristic evolutionary algorithms for the design of optimal multiplier-less recombination filter banks

This paper proposes a design for multiplier-less recombination non-uniform filter banks (RNUFBs) optimized using meta-heuristic algorithms. The structure consists of an M-channel uniform filter bank, with some channels combined by the synthesis filters of a transmultiplexer (TMUX), yielding non-uniform sub-bands. When any structure is realized in hardware, it is necessary to have low power consumption and a small chip area. These can be achieved by replacing the multipliers with shifters and adders. Once the continuous coefficient recombination non-uniform filter bank is designed, the coefficients are converted to the canonic-signed-digit (CSD) space to make the design multiplier-less, so as to reduce the complexity of the hardware implementation. To reduce the number of adders and shifters in the multiplier-less implementation, the filter coefficients are rounded with a restricted number of signed power-of-two (SPT) terms, which may cause degradation in the performance of the RNUFBs. To improve the performance of the CSD rounded filters and filter bank, meta-heuristic algorithms such as the artificial bee colony (ABC) algorithm, harmony search algorithm (HSA) and gravitational search algorithm (GSA) are deployed. Of these meta-heuristic algorithms, GSA is found to give the best performance. The method proposed in this paper results in non-uniform filter banks with rational sampling factors which are multiplier-less and have linear-phase and near-perfect-reconstruction.

Adjustable window based design of multiplier-less cosine modulated filter bank using swarm optimization algorithms

In this paper, an adjustable window based approach is presented for the design of multiplier-less near perfect reconstruction cosine modulated filter bank (CMFB) for specified stopband attenuation (As) and channel overlapping. Kaiser window function is employed for designing the computationally efficient prototype filter with filter coefficients in canonic signed digit (CSD) space. Optimized performance of the designed filter is achieved using swarm based algorithm such as cuckoo search (CS) optimization, so that the filter coefficients of a multiplier-less prototype filter are optimized to achieve the magnitude response of 0.707 at frequency ω=π/2M. In this method, instead of using two optimization techniques: one for designing continuous coefficients and other for optimizing quantized prototype filter coefficients, single swarm based technique is used, while a comparative study using proposed scheme based on the performance of different window functions as well as different swarm based techniques such particle swarm optimization (PSO) and artificial bee colony (ABC) algorithm is made. Design examples presented, using this technique, illustrates the improved performance of proposed technique as compared to other published algorithms.

희소한 부호 자리수 계수를 갖는 FIR 필터 설계

광대역 통신 모뎀이나 초고해상도 비디오 코덱 등과 같이 높은 데이터율을 갖는 시스템을 하드웨어로 구현할 때에는 디지털 필터의 고속 구현이 필수적이다. 디지털 필터의 임계경로는 대부분 MAC (multiplication and accumulation) 연산 회로이므로 필터 계수의 0이 아닌 비트의 갯수가 희소하다면 하드웨어 비용이 적은 덧셈기로도 디지털 필터를 고속으로 구현할 수 있다. 압축센싱은 신호의 희소 표현이나 희소 신호의 복원에 우수한 성능을 보임이 최근 연구에서 보고되고 있다. 본 논문에서는 압축센싱에 기반한 디지털 FIR 필터의 CSD (canonic signed digit) 계수를 찾는 방법을 제안한다. 주어진 주파수 응답과의 오차를 최소하면서 탐욕적 방법으로 희소한 0이 아닌 부호자리수를 찾고 잘못 선택되었던 부호자리수는 제거하는 과정을 반복한다. 설계 예를 통해 제안된 방법으로 희소한 0이 아닌 CSD 계수의 FIR 필터를 설계할 수 있음을 보인다. High speed implementation of digital filters is required in high data rate applications such as hard-wired wide band modem and high resolution video codec. Since the critical path of the digital filter is the MAC (multiplication and accumulation) circuit, the filter coefficient with sparse non-zero bits enables high speed implementation with adders of low hardware cost. Compressive sensing has been reported to be very successful in sparse representation and sparse signal recovery. In this paper a filter design method for digital FIR filters with CSD (canonic signed digit) coefficients using compressive sensing technique is proposed. The sparse non-zero signed bits are selected in the greedy fashion while pruning the mistakenly selected digits. A few design examples show that the proposed method can be utilized for designing sparse CSD coefficient digital FIR filters approximating the desired frequency response.

Design of Digital Filters for Multi-standard Transceivers

This paper addresses on three different architectures of digital decimation filter design of a multi-standard RF transceivers. Instead of using single stage decimation filter network, the filters are implemented in multiple stages using FPGA to optimize the area, delay and dynamic power consumption. The proposed decimation filter architectures reflect the considerable reduction in area and dynamic power consumption without degradation of performance. The filter coefficients are derived from MATLAB, the filter architectures are implemented and tested using Xilinx SPARTAN FPGA .First, the types of decimation filter architectures are tested and implemented using conventional binary number system. Then the two different encoding schemesi.e. Canonic Signed Digit (CSD) and Minimum Signed Digit (MSD) are used for filter coefficients and then the architecture performances are tested .The results of CSD and MSD based architectures show a considerable reduction in the area and power against the conventional number system based filter design implementation. The implementation results reflect that considerable reduction in area of 47.89% and dynamic power reduction of 28.64% are achieved using hybrid architecture.

Design of multiplier-less sharp non-uniform cosine modulated filter banks for efficient channelizers in software defined radio

Forthcoming software defined radios require filter banks which satisfy stringent specifications efficiently with low implementation complexity. Cosine modulated filter banks (CMFB) have simple and efficient design procedure. The different wireless standards have different channel spacing or bandwidths and hence demand non-uniform decomposition of subbands. The non-uniform CMFB can be obtained from a uniform CMFB in a simple and efficient approach by merging the adjacent channels of the uniform CMFB. Very narrow transition width filters with low complexity can be achieved using frequency response masking (FRM) filter as prototype filter. The complexity is further reduced by the multiplier-less realization of filter banks in which the least number of signed power of two (SPT) terms is achieved by representing the filter coefficients using canonic signed digit (CSD) representation and then optimizing using suitable modified meta-heuristic algorithms. Hybrid meta-heuristic algorithms are used in this paper. A hybrid algorithm combines the qualities of two meta-heuristic algorithms and results in improved performances with low implementation complexity. Highly frequency selective filter banks characterized by small passband ripple, narrow transition width and high stopband attenuation with non-uniform decomposition of subbands can be designed with least the implementation complexity, using this approach. A digital channelizer can be designed for SDR implementations, using the proposed approach. In this paper, the non-uniform CMFB is designed for various existing wireless standards.