DAC Calibration Research Articles

An 18-bit SAR ADC with Mixed DAC and Capacitive Recombination Calibration

An 18-bit SAR ADC with Mixed DAC and Capacitive Recombination Calibration

A Model-Based Approach Digital Pre-Distortion Method for Current-Steering Digital-to-Analog Converters

This paper presents a novel static digital pre-distortion (DPD) method for a current-steering digital-to-analog converter (CS-DAC). The proposed method utilizes the knowledge of the current cell array architecture to calculate the static mismatch currents of the cells. The mismatch values are stored in memory and added to the original input code to generate the new pre-distorted input word. The converter corrects the static error with its own current cells without incorporating an additional calibration DAC (CALDAC) or programmable current sources. This results in a reduction in area, power and simulation run times because of the simpler circuit design. An Overflow-Cell-Selection (OCS) is introduced as a novel solution to further enhance the static linearity of the converter. It also can be implemented as a software solution for already existing DAC designs which do not have an integrated DPD and lab/measurement equipment (e.g., arbitrary wave generator (AWG)). This poses as a strong differentiation factor compared to other state-of-the-art static DPD methods. The evaluation of the proposed DPD is done via simulations in MATLAB and on- chip measurements with a 14-bit CS-DAC in 16 nm. Single tone measurements show a performance gain of the total harmonic distortion (THD) of 12 dB.

Noise-Shaping SAR ADC Using a Two-Capacitor Digitally Calibrated DAC With 82.6-dB SNDR and 90.9-dB SFDR

A novel active noise-shaping SAR ADC with on- chip digital DAC calibration is presented. To relax the design of the single op-amp used as an integrator, correlated double sampling (CDS) and correlated level shifting (CLS) were implemented. CDS minimizes the offset of the integrator and reduces the flicker noise, while CLS boosts the gain of the op-amp and reduces the power consumption. Also, a two-step incremental ADC based digital DAC calibration scheme was implemented to cancel the DAC mismatch errors and parasitics effects. The ADC was fabricated in 0.13 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS technology. It achieved 85.1 dB DR, 82.6 dB SNDR and 90.9 dB SFDR within a 2 kHz signal bandwidth with an oversampling ratio OSR = 32. It consumes 40.8 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> power using a 1.6 V power supply.

A Simple Histogram-Based Capacitor Mismatch Calibration in SAR ADCs

This brief presents a simple capacitor mismatch calibration in SAR ADCs, which is in foreground and on chip. Capacitor errors are extracted based on output histogram under a triangular input signal generated on chip and compensated by tuning capacitors with a calibration DAC. A novel one-by-one strategy can simplify the extraction by isolating the individual contribution of each capacitor error. The proposed calibration needs no computation and is validated with a 10-bit 100MS/s SAR ADC. Size of the ADC core including calibration system is only $90\mu \text{m}\times 97\mu \text{m}$ . Measurement results show effectiveness of the proposed calibration.

A novel design of hybrid-time-interleaved current steering digital to analog converter and its behavioral simulation considering non-ideal effects

This work presents a behavioral model for non-ideal effects in a novel Hybrid time-interleaved digital to analog converter (TIDAC). In Hybrid DACs, both ΔΣ and Nyquist structures are used. In this work, in the Nyquist path, the 2-time-interleaving technique is used and in the ΔΣ path, a new structure is proposed to reduce the critical path in the TI delta-sigma modulator (DSM). In conventional TIDSM, adding each channel to the structure leads to increasing the critical path as one full-adder. This, in turn, decreases the speed of modulator since a single feedback loop is utilized to compute the running sum of the input signals. In this work, a new type of poly-phase decomposition is presented that keeps the critical path for each number of channels constant and minimizes the number of full-adders. Simulations are performed on 4-TI-MASH 1-1 and Hybrid-TI current steering-DAC (CS-DAC) using an analytical behavioral model in presence of non-ideal effects. In order to realize non-ideal effects, a SIMULINK model for clock jitter error is proposed and added to the other types of error. Furthermore, a model for estimation of duty-cycle-error (DCE) is presented and utilized for calibration. Simulation results show that the proposed TIDSM has a good performance in MASH 1-1 modulator with the 20dB/dec noise shaping. Simulated error behaviors make a good insight into designing the DAC circuit parameters and calibration method.

A 12-bit 220-MS/s Area-efficient DAC in 65 nm CMOS with Calibration-DAC Assisted Linearity Enhancement

An area-efficient 12-bit current-steering DAC in 65 nm CMOS with a 3rd-order harmonic canceling calibration DAC is presented. The calibration DAC removes cubic error caused by finite output impedance by injecting correction current corresponding to the opposite of the INL error. To more effectively enable the calibration, the DAC adopts a return-to-zero signaling that suppresses the signal frequency dependency. The prototype DAC occupies an active area of 0.13 mm² while dissipating 59 mW from 1.2 V/1.8 V supply. The calibration DAC achieves 3rd-order harmonic reduction of as much as 15.8 dB up to Nyquist frequency when running at the sampling frequency of 220 MS/s.

A −89-dBc IMD3 DAC Sub-System in a 465-MHz BW CT Delta-Sigma ADC Using a Power and Area Efficient Calibration Technique

This brief presents a power and area efficient way to measure the feedback DAC static mismatch error in a multi-bit continuous-time delta-sigma modulator. By sequentially forcing each DAC element output in the designed scheme, the mismatch errors among DAC elements can be measured digitally using the ADC itself. The measured errors are then corrected using a two-parameter calibration DAC that tracks temperature variations. An ADC test chip is fabricated in 28-nm CMOS process and it demonstrates IMD3 <−89 dBc with two −9-dBFS tones at 180/190 MHz at room temperature, and 8 dB variation across −10 °C to 120 °C.

A low-cost digital-domain foreground calibration for high resolution SAR ADCs

A digital-domain foreground calibration method simultaneously correcting mismatch errors in main capacitive digital to analog converter (CDAC) and “segment error” between main CDAC and sub-CDAC of split-CDAC array in high resolution successive approximation register (SAR) analog-to-digital converter (ADC) is proposed. The actual weight is obtained with the digital-domain weight estimation algorithm. This proposed digital-domain calibration saves silicon area by eliminating the need for a dedicated calibration DAC employed in conventional CDAC mismatch calibration schemes. Behavioral simulation shows the proposed calibration is capable of correcting mismatch errors and “segment error” of split-CDAC array, and improving SNDR from 67.3 dB to 92.8 dB in a prototype 16 bit split-CDAC SAR ADC.

A CMOS Current Steering Neurostimulation Array With Integrated DAC Calibration and Charge Balancing.

An 8-channel current steerable, multi-phasic neural stimulator with on-chip current DAC calibration and residue nulling for precise charge balancing is presented. Each channel consists of two sub-binary radix DACs followed by wide-swing, high output impedance current buffers providing time-multiplexed source and sink outputs for anodic and cathodic stimulation. A single integrator is shared among channels and serves to calibrate DAC coefficients and to closely match the anodic and cathodic stimulation phases. Following calibration, the differential non-linearity is within ±0.3 LSB at 8-bit resolution, and the two stimulation phases are matched within 0.3%. Individual control in digital programming of stimulation coefficients across the array allows altering the spatial profile of current stimulation for selection of stimulation targets by current steering. Combined with the self-calibration and current matching functions, the current steering capabilities integrated on-chip support use in fully implanted neural interfaces with autonomous operation for and adaptive stimulation under variations in electrode and tissue conditions. As a proof-of-concept we applied current steering stimulation through a multi-channel cuff electrode on the sciatic nerve of a rat.

A self-calibration method for capacitance mismatch in SAR ADC with split-capacitor DAC

A self-calibration method to calibrate the nonlinearity due to capacitance mismatch in successive approximation register (SAR) analog-to-digital converter (ADC) is presented. It focuses on calibrating the most significant bit (MSB) array in the split-capacitor main DAC (split-MDAC) by using a calibration DAC (CDAC) that contains multiple sub-CDACs. Every bit in MSB array has its corresponding sub-CDAC in CDAC, which enhances the calibration efficiency. To verify the calibration method, a 14 bit, 500kS/s SAR ADC is implemented, and it is manufactured in 0.35μm 2P4M CMOS process. The measured results show that the proposed calibration method can assist this SAR ADC to achieve better static and dynamic performance, and its ENOB is improved from 9 bit to 11.98 bit at Nyquist input frequency.

An ECG recording front-end with continuous-time level-crossing sampling.

An ECG recording front-end with a continuous- time asynchronous level-crossing analog-to-digital converter (LC-ADC) is proposed. The system is a voltage and current mixed-mode system, which comprises a low noise amplifier (LNA), a programmable voltage-to-current converter (PVCC) as a programmable gain amplifier (PGA) and an LC-ADC with calibration DACs and an RC oscillator. The LNA shows an input referred noise of 3.77 μVrms over 0.06 Hz-950 Hz bandwidth. The total harmonic distortion (THD) of the LNA is 0.15% for a 10 mVPP input. The ECG front-end consumes 8.49 μW from a 1 V supply and achieves an ENOB up to 8 bits. The core area of the proposed front-end is 690 ×710 μm2, fabricated in a 0.18 μm CMOS technology.

A SAW-Less Receiver Front-End Employing Body-Effect Control IIP2 Calibration

An IM2 product cancellation technique that employs a body-effect control of transistors is presented by developing a design for low-cost and high-linearity receiver front-end in LTE/WCDMA applications. To accomplish a high IIP2 for strong out-of-band blockers, the body terminal voltage of the mixer switches is properly adjusted to provide intentional asymmetry and suppress the IM2 at the mixer output. Without the usage of inter-stage SAW filters, an out-of-band IIP2 of better than +60 dBm is consistently attained under different operating frequencies and channel bandwidths by applying this technique. Only 5-bits DAC calibration codes are utilized. The receiver front-end is implemented in a 65-nm CMOS technology and achieves out-of-band IIP3s of 3 dBm, 3.9 dBm and 5.4 dBm; in-band IIP3s of -8.4 dBm, -9.2 dBm and -10.5 dBm; out-of-band P1dBs of -24 dBm, -22 dBm and -21 dBm; peak gains of 42.5 dB, 41 dB and 42.2 dB; and double side-band noise figures of 2.3 dB, 2.7 dB and 2.4 dB for Band 2 (LTE), Band 7 (LTE) and Band 1 (WCDMA), respectively. It operates at a nominal supply voltage of 1.2 V with bias currents of 15.1 mA, 17 mA and 14.2 mA, respectively. The active die area is 1.45 mm 2 .

A 20b Clockless DAC With Sub-ppm INL, 7.5 nV/√Hz Noise and 0.05 ppm/°C Stability

This paper presents a 20b clockless DAC designed for precision calibrated systems. The architecture is a 6b parallel resistor voltage divider with a 14b R-2R subDAC. This architecture is inherently good for noise and temperature stability. Major causes of nonlinearity are discussed. A single current-output calibration DAC corrects for both random resistor mismatch and systematic resistor nonlinearity. A force and sense switch topology overcomes INL from CMOS switch resistance. The DAC is implemented in a 0.6 μm 30 V BiCMOS process with 5 V CMOS devices and Si-Cr thin-film resistors. It achieves 0.33 ppm INL and 7.5 nV/√Hz noise with a ±10 V output span. It has 0.05 ppm/°C temperature stability and settles in 1 μs. Current consumption is 4.2 mA from 30 V supplies, excluding power required for external reference buffers.

A 10.3-GS/s, 6-Bit Flash ADC for 10G Ethernet Applications

This paper presents the design of a 40-nm CMOS 10.3-GS/s 6-bit Flash ADC used as the analog frontend of a universal DSP-based receiver that meets the requirements for all the NRZ 10G Ethernet (10GE) standards, for both fiber and copper channels. The 4-way interleaved ADC consists of a pair of frontend variable gain amplifiers (VGAs) driving four sets of track-and-hold (T/H) switches, followed by fine VGAs that drive 6-bit comparator arrays. A Wallace-tree adder is utilized as the thermometer-to-binary encoder allowing comparator re-ordering and redundancy. Also integrated is an 8-bit calibration DAC that is used as a reference to nullify the accumulated offset of the entire signal path, as well as to compensate for the nominal nonlinearity of the fine VGA and the resistor ladder. After calibration, the peak SNDR of the ADC is about 34 dB with bandwidth ranging from 3.5 to 6 GHz over all VGA gain settings. The ADC, along with its entire clock path, occupies 0.27 mm <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$^{2}$</tex></formula> and consumes 242 mW from a 0.9-V supply.

Design considerations of calibration DAC in self-calibrated SAR A/D converters

A capacitive calibration digital-to-analog converter (CDAC) is commonly used to reduce the mismatch-induced linearity errors for successive approximation register (SAR) analog-to-digital converters (ADC) employing capacitor arrays. There are complicated design considerations in determining the number of bits, the unit capacitor value and even the parasitic capacitors of the CDAC, as these factors affect or are determined by the achievable ADC resolution, the main DAC's capacitance, and the main DAC unit capacitance value, etc. This paper is the first to present a systematic analysis on these relationships. The analysis is validated by behavioral and circuit simulation results.

Self‐calibrated SAR ADC based on split capacitor DAC without the use of fractional‐value capacitor

AbstractA successive approximation register analog‐to‐digital converter (SAR ADC) based on a split‐capacitor digital‐to‐analog converter (CDAC) with a split binary weighted capacitor array and C‐2C ladder is proposed. In present design, a unit split capacitor is used in the CDAC instead of the fractional‐value capacitor in the conventional configuration. The preset error induced by the unit split capacitor and the mismatch error of the upper bit CDAC are self‐calibrated. The calibration range and the impact of calibration DAC resolution on circuit linearity are studied to provide an optimum design guideline. Behavior simulation and post‐layout simulation are performed to verify the proposed calibration method. © 2013 Institute of Electrical Engineers of Japan. Published by John Wiley &amp; Sons, Inc.

A 10-bit 50-MS/s reference-free low power SAR ADC in 0.18-μm SOI CMOS technology

A 10-bit 50-MS/s reference-fee low power successive approximation register (SAR) analog-to-digital converter (ADC) is presented. An energy efficient switching scheme is utilized in this design to obtain low power and high frequency operation performance without an additional analog power supply or on-chip/off-chip reference. An on-chip calibration DAC (CDAC) is implemented to cancel the offset of the latch-type sense amplifier (SA) to ensure precision whilst getting rid of the dependence on the pre-amplifier, so that the power consumption can be reduced further. The design was fabricated in IBM 0.18-μm 1P4M SOI CMOS process technology. At a 1.5-V supply and 50-MS/s with 5-MHz input, the ADC achieves an SNDR of 56.76 dB and consumes 1.72 mW, resulting in a figure of merit (FOM) of 61.1 fJ/conversion-step.

Digital DAC calibration technique for ΔΣ and incremental modulators

A new digital nonlinearity calibration and correction technique is proposed for multi-bit DACs in ΔΣ and incremental modulators. By finding the differences between capacitance errors using the ΔΣ modulator, the integral nonlinearity of the DAC can be found, and corrected digitally.

Calibration technique for SAR analog-to-digital converters

A self-calibration technique was developed for SAR analog-to-digital converters that employ binary-weighted capacitors. High-accuracy calibration is achieved by finding and correcting the mismatch of each capacitor independently. The mismatch errors are extracted at power-up, and corrected by individual calibration DACs during the conversion. Unlike in previous schemes, in the proposed method the residual error in the calibration of a capacitor does not affect the calibration of any other capacitor. Simulation results show that the proposed method is also insensitive to the non-idealities of the calibration DACs.

A digital calibration technique for an ultra high-speed wide-bandwidth folding and interpolating analog-to-digital converter in 0.18-μm CMOS technology

A digital calibration technique for an ultra high-speed folding and interpolating analog-to-digital converter in 0.18-μm CMOS technology is presented. The similar digital calibration techniques are taken for high 3-bit flash converter and low 5-bit folding and interpolating converter, which are based on well-designed calibration reference, calibration DAC and comparators. The spice simulation and the measured results show the ADC produces 5.9 ENOB with calibration disabled and 7.2 ENOB with calibration enabled for high-frequency wide-bandwidth analog input.