Abstract
AbstractA successive approximation register analog‐to‐digital converter (SAR ADC) based on a split‐capacitor digital‐to‐analog converter (CDAC) with a split binary weighted capacitor array and C‐2C ladder is proposed. In present design, a unit split capacitor is used in the CDAC instead of the fractional‐value capacitor in the conventional configuration. The preset error induced by the unit split capacitor and the mismatch error of the upper bit CDAC are self‐calibrated. The calibration range and the impact of calibration DAC resolution on circuit linearity are studied to provide an optimum design guideline. Behavior simulation and post‐layout simulation are performed to verify the proposed calibration method. © 2013 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.
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