A 12-bit 220-MS/s Area-efficient DAC in 65 nm CMOS with Calibration-DAC Assisted Linearity Enhancement

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An area-efficient 12-bit current-steering DAC in 65 nm CMOS with a 3rd-order harmonic canceling calibration DAC is presented. The calibration DAC removes cubic error caused by finite output impedance by injecting correction current corresponding to the opposite of the INL error. To more effectively enable the calibration, the DAC adopts a return-to-zero signaling that suppresses the signal frequency dependency. The prototype DAC occupies an active area of 0.13 mm² while dissipating 59 mW from 1.2 V/1.8 V supply. The calibration DAC achieves 3rd-order harmonic reduction of as much as 15.8 dB up to Nyquist frequency when running at the sampling frequency of 220 MS/s.