A 10.3-GS/s, 6-Bit Flash ADC for 10G Ethernet Applications

Abstract

This paper presents the design of a 40-nm CMOS 10.3-GS/s 6-bit Flash ADC used as the analog frontend of a universal DSP-based receiver that meets the requirements for all the NRZ 10G Ethernet (10GE) standards, for both fiber and copper channels. The 4-way interleaved ADC consists of a pair of frontend variable gain amplifiers (VGAs) driving four sets of track-and-hold (T/H) switches, followed by fine VGAs that drive 6-bit comparator arrays. A Wallace-tree adder is utilized as the thermometer-to-binary encoder allowing comparator re-ordering and redundancy. Also integrated is an 8-bit calibration DAC that is used as a reference to nullify the accumulated offset of the entire signal path, as well as to compensate for the nominal nonlinearity of the fine VGA and the resistor ladder. After calibration, the peak SNDR of the ADC is about 34 dB with bandwidth ranging from 3.5 to 6 GHz over all VGA gain settings. The ADC, along with its entire clock path, occupies 0.27 mm <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$^{2}$</tex></formula> and consumes 242 mW from a 0.9-V supply.