Cadence Software Research Articles

Area Efficient Modified Array Multiplier

Multipliers are widely used for various application like signal processing. Multipliers are used for multiplication two binary data .There are different kinds of multipliers with their own advantages and disadvantages. In this paper we implemented Array multiplier which has considerably more speed but also more area, it was implemented using pseudo NMOS logic in Cadence software and the number of transistors was reduced from 2N to N+1 which also lead to reduction in area.

OTA-C Realization of An Optimized FOPID Controller for BLDC Motor Speed Control

The paper presents the design and circuit realization of an optimized fractional-order PID controller (FOPID) for speed control of a permanent magnet brushless direct current (BLDC) motor. Here, the FOPID controller is designed using the Nelder-Mead optimization algorithm. The servo-regulatory performance of the BLDC motor using the FOPID controller is compared with integer-order PID controllers, which are designed using tuning methods like Ziegler Nichols, Astrom-Hagglund, Cohen-Coon, and Chien-Hrones-Reswick method. The FOPID controller circuit is realized using Operational Transconductance Amplifiers (OTAs) and capacitors in Cadence Virtuoso Analog Design Environment using GPDK 180 nm technology and simulated using Spectre circuit simulator. The circuit realization is based on the multiple-loop-feedback structure. The OTA-C realization facilitates advantages like electronic tunability, resistor-less, and on-chip realization capability. The time and frequency domain performance measures of the OTA-C FOPID controller with the BLDC motor are evaluated using the Cadence software and compared with the theoretical plots. Finally, a modified OTA-C circuit with reduced active element count is used, and its performance is evaluated.

Electronically tunable mixed mode universal filter employing grounded capacitors utilizing highly versatile VD-DVCC

PurposeThis paper aims to achieve two main objectives. First, to introduce to the literature a new versatile active building block, namely, voltage differencing differential voltage current conveyor (VD-DVCC) for analog signal processing applications. Second, to design a novel electronically tunable mixed-mode universal filter. The designed filter provides low-pass, high-pass, band-pass, band-reject and all-pass responses in voltage-mode (VM), current-mode (CM), trans-impedance-mode (TIM) and trans-admittance-mode (TAM).Design/methodology/approachThe proposed filter uses two VD-DVCCs, three resistors and two capacitors. All the capacitors used are grounded, which is advantageous from the monolithic integration point of view. The VD-DVCC is designed and validated in Cadence software using CMOS 0.18 µm process design kit from Silterra Malaysia at a supply voltage of ±1 V.FindingsThe proposed novel filter enjoys many attractive features including as follows: the ability to operate in all four modes, no requirement of capacitive matching, tunability of quality factor (Q) independent of pole frequency, availability of both inverting and non-inverting outputs for VM and TIM mode, high output impedance explicit current output for CM and TAM, no requirement for double/negative input signals (voltage/current) for response realization and low active and passive sensitivities. The filter is designed for a pole frequency of 5.305 MHz. The obtained results bear a close resemblance with the theoretical findings.Originality/valueThe proposed novel filter structure requires a minimum number of active and passive components and provides operation in all four operating modes. The filter will find application in structures of mixed-mode systems.

A high efficiency and high speed charge of Li-Ion battery charger interface using switching-based technique in 180 nm CMOS technology

In this work, the design and analysis of new Li-Ion battery charger interface using the switching-based technique is proposed for high efficiency, high speed charge and low area. The high efficiency, the lower size area and the fast charge are the more important norms of the proposed Li-Ion battery charger interface. The battery charging is completed passes to each charging mode: The first mode is the trickle charge mode (TC), the second mode is the constant current mode (CC) and the last mode is the constant voltage mode (CV), in thirty three minutes. The new Li-Ion battery charger interface is designed, simulated and layouted in Cadence software using TSCM 180 nm CMOS technology. With an input voltage V<sub>IN</sub> = 4.5 V, the output battery voltage (V<sub>BAT</sub>) may range from 2.7 V to 4.2 V and the maximum charging battery current (I<sub>BAT</sub>) is 1.7 A. The peak efficiency reaches 97% and the total area is only 0.03mm<sup>2</sup> .

A Linear 0.98 mV Low-Dropout Voltage Regulator in 0.18-μm CMOS Technology

This paper presents a linear low-dropout (LDO) voltage regulator in 0.18-pm CMOS technology. The proposed LDO consists of voltage reference, error amplifier, pass device, output capacitor and resistive feedback network. A symmetrical operational transconductance amplifier (OTA) is implemented as an error amplifier and a PMOS transistor is used as a pass device to produce low dropout voltage and low quiescent current. The proposed design is simulated using Spectre simulator in Cadence software to verify its performances. The simulation results indicated that the LDO regulator achieves a regulated output voltage of 1.5 V with the ranges of supply voltage from 1.7 V to 2.0 V. The LDO regulator has a dropout voltage of 19.3 mV under maximum load current of 1.1 mA. The proposed LDO regulator is suitable for power management system.

Synthesis of biquad filters using two VD-DIBAs with independent control of quality factor and natural frequency

This contribution presents the procedure to synthesis the voltage-mode active biquad filters using the active elements, voltage differencing differential input buffered amplifier (VD-DIBA). Two filtering categories, single input four output (SIFO) configuration and three input three output (TITO) configuration are proposed. Both proposed filters consist of two VD-DIBAs, two grounded capacitors and two resistors. All input voltage nodes for both biquad filters exhibit high impedance. The proposed SIFO biquad filter simultaneously provide four filtering responses, low pass (LP), band pass (BP), high pass (HP) and band reject (BR) functions, while the proposed TITO filter provides five filtering responses (including all pass (AP) function). The natural frequency (ω0) is linearly and electronically tuned without affecting the quality factor (Q). Also, the Q adjusting can be done without affecting the ω0. By modifying the proposed TITO biquad filter, the current controlled sinusoidal oscillator is achieved. The frequency of the generated sinewave is linearly tuned without affecting the condition of oscillation. The performances of the proposed circuits are simulated by Cadence software and the Spectre simulator of the Analog Design Environment using CMOS VD-DIBA in 0.18 μm TSMC CMOS technology and laboratory experiment using VD-DIBA constructed from commercially available ICs.

Design of PWM-Based Digital Receiver for 5G

The next generation, 5G and 6G standards, are allocated different bands for the same standard due to the worsening shortage of available spectrum. This has led to significant research interest in digitizing the RF signal as close as possible to the antenna motivated by flexibility and high performance allowed by cognitive radio and software defined radio. In this paper, a PWM-based all digital receiver is Presented. A system level simulation of the pulse-width modulator is performed using cadence software. In addition, a high-speed two-stage dynamic CMOS-latched comparator is proposed. In addition, a high-speed ring oscillator for clock generation is given. The proposed pulse-width modulator is implemented with a target technology TSMC 65nm process. The comparator achieves sampling frequency up to 10 GHz with resolution of 10.11 bits and 13.28 bits at 1 GHz sampling clock while keeping the propagation delay less than 64 psec. for 1 mV input voltage difference. Furthermore, the oscillator achieves a 10.025GHz output frequency.

Low power pulsed flip-flop with clock gating and conditional pulse enhancement

A clock system consumes above 25% of the total system power. Flip-flops (FFs) are widely used as the basic storage element in all kinds of digital structures. The use of pulse-triggered flip-flops (P-FFs) in digital design provides better performance than conventional flip-flop designs. This paper presents the design of a new power-efficient implicit pulse-triggered flip-flop suitable for low power applications. Two important features are embedded in this flip-flop architecture. Firstly, the enhancement in width and height of trigger pulses during specific conditions gives a solution for the longest discharging path problem in existing P-FFs. Secondly, the clock gating concept reduces unwanted switching activities at sleep/idle mode of operation and thereby reducing dynamic power consumption. The post-layout simulation results in cadence software based on CMOS 90 nm technology shows that the proposed design features less power dissipation and better power delay performance (PDP) when compared with conventional P-FFs. This paper also presents a comparative study on the performance of implicit and explicit pulse flip-flop designs. The maximum power saving of proposed design against conventional implicit and explicit design is up to 18.45% and 58.49%, respectively.

Low power pulsed flip-flop with clock gating and conditional pulse enhancement

A clock system consumes above 25% of the total system power. Flip-flops (FFs) are widely used as the basic storage element in all kinds of digital structures. The use of pulse-triggered flip-flops (P-FFs) in digital design provides better performance than conventional flip-flop designs. This paper presents the design of a new power-efficient implicit pulse-triggered flip-flop suitable for low power applications. Two important features are embedded in this flip-flop architecture. Firstly, the enhancement in width and height of trigger pulses during specific conditions gives a solution for the longest discharging path problem in existing P-FFs. Secondly, the clock gating concept reduces unwanted switching activities at sleep/idle mode of operation and thereby reducing dynamic power consumption. The post-layout simulation results in cadence software based on CMOS 90 nm technology shows that the proposed design features less power dissipation and better power delay performance (PDP) when compared with conventional P-FFs. This paper also presents a comparative study on the performance of implicit and explicit pulse flip-flop designs. The maximum power saving of proposed design against conventional implicit and explicit design is up to 18.45% and 58.49%, respectively.

Design of low power VCO using FinFET technology for biomedical applications

A voltage controlled oscillator (VCO) is one of the most significant essential structure obstructs in simple and advanced circuit (CKT). In Biomedical applications the nature of the biomedical connection is resolved in huge part by the qualities of the VCO and in the present biomedical applications more prominent recurrence goes is required by the VCOs. Generally, VCOs utilizing CMOS innovation have been utilized for low recurrence applications, however 18 nm forms have permitted CMOS oscillators to accomplish frequency in the gigahertz extend. This range is made conceivable with the utilization of programmed swing control. VCO can be fabricated utilizing many CKT strategies. VCO can be built using many CKT techniques. To design improved performance VCO’s explicitly low power different techniques using latest cadence software to obtain high density and low leakage current. To optimize and design the VCs, carry out analysis and enhance the performance. To design VCO with four different techniques using latest cadence software, optimize their performance and measure it in cadence software environment.

Field programmable Gate Array based Real Time Object Tracking using Partial Least Square Analysis

In this paper, we proposed an object tracking algorithm in real time implementation of moving object tracking system using Field programmable gate array (FPGA). Object tracking is considered as a binary classification problem and one of the approaches to this problem is that to extract appropriate features from the appearance of the object based on partial least square (PLS) analysis method, which is a low dimension reduction technique in the subspace. In this method, the adaptive appearance model integrated with PLS analysis is used for continuous update of the appearance change of the target over time. For robust and efficient tracking, particle filtering is used in between every two consecutive frames of the video. This has implemented using Cadence and Virtuoso software integrated environment with MATLAB. The experimental results are performed on challenging video sequences to show the performance of the proposed tracking algorithm using FPGA in real time.

A VERY LOW-DROPOUT VOLTAGE REGULATOR IN 0.18-M CMOS TECHNOLOGY FOR POWER MANAGEMENT SYSTEM

This paper proposes the design of a very low-dropout (LDO) voltage regulator in 0.18-mm CMOS technology. The proposed LDO regulator consists of voltage reference, symmetrical operational transconductance amplifier (OTA), PMOS transistor, resistive feedback network and output capacitor. The NMOS symmetrical OTA is implemented as an error amplifier and a PMOS transistor is employed as a pass device to improve gain and minimize low dropout voltage, respectively. The proposed design is simulated using Spectre simulator in Cadence software to verify its regulator performance. The simulation results show that the proposed LDO is capable to operate from a supply voltage of 1.7-2.0 V with a low dropout voltage of 19.3 mV at a maximum 50 mA load current to regulate output voltage 1.5 V. The active chip is 2.96 mm2 in size. The performance of the proposed LDO is suitable to enhance power management for system on chip (SoC) applications.

Comparative Study and Design of Current Starved Ring Oscillators in 16 nm Technology

In this brief, different characteristics of current starved ring oscillator (CSRO) circuits are investigated and four new designs are proposed. A new parameter, known as phase noise bandwidth product (PNBP), is also proposed to address the trade-off between phase noise performance and frequency tuning range while designing ring oscillators (ROs). The proposed circuits are compared with existing architectures in terms of power consumption, frequency bandwidth, maximum frequency, phase noise, power delay product (PDP) and PNBP. For performance evaluation, three-stage CSROs have been implemented in Cadence software using the 16 nm PTM High Performance (HP) technology model. Simulation results demonstrate that two newly proposed CSRO architectures using one NMOS sink or one PMOS source have similar optimum results in terms of PDP and PNBP as the existing CSRO using an output switch scheme, but with an advantage of lower area requirement. Moreover, all four proposed architectures show improved performance in terms of PDP and PNBP compared to conventional CSRO. The performance of the CSROs is also observed and compared with respect to the variations in process-voltage-temperature (PVT) parameters.

Implementation and analysis of tunable fractional-order band-pass filter of order 2α

This paper proposes a new design of a 2α-order fractional-order band-pass filter with tunability feature. The proposed filter is approximated with the Continued Fraction Expansion and Matsuda second-order approximations. The realized filter transfer function is based on the Inverse Follow the Leader Feedback configuration, with Operational Transconductance Amplifiers as active elements. As a result, the order of the proposed filter can be adjusted by changing a single parameter, which is the bias current Ibias. A comparison with the previous works is performed, showing the advantage of the electronic tuning feature using one bias current value in the proposed filter. Sensitivity analysis is conducted to investigate the effect of circuit parameters variation, such as capacitance and gain factors. Stability analysis is performed by studying the poles’ location and movement versus the filter parameters. Besides, the effect of transistor mismatch is evaluated using Monte Carlo analysis. Matlab and Cadence software, with UMC technology of 0.13 μm CMOS, are used for verifying the proposed implementation.

Design of 0.13 µm low power CMOS subharmonic mixer for DCR applications

ABSTRACT This paper presents a design of 2.4 GHz folded subharmonic active mixer in TSMC 130 nm CMOS process for direct conversion receiver (DCR). To achieve the low supply voltage, the folded topology is adopted for the proposed subharmonic mixer. The complementary current reuse structure is used as RF transconductance stage where the biasing for the PMOS and NMOS transistors are self-biased by a resistor to support high conversion gain at low supply voltage. Frequency doubling operation is done by the mixing core which is driven by a quadrature local oscillator (LO) signals. The proposed mixer is designed and simulated using ADS (Advanced Design System) simulator with Cadence software. It produces 10.5 dB conversion gain, a single sideband) noise figure of 9.5 dB, 2 LO-to-RF isolation of 53 dB, LO-to-RF isolation of 117 dB, RF-to-IF isolation of 55 dB and IIP3 of −7.5 dBm. The quadrature LO subharmonic mixer consumes 824μW power from a supply voltage of 0.8 V. The proposed mixer is compared with existing subharmonic mixers. The comparison shows the proposed subharmonic mixer gives a good Figure of Merit.

Minimization of power and area of digital modulator for cellular communication using cadence in 180nm, 90nm and 45nm CMOS technology

Background/Objectives: Low power modulators are most efficient for wireless communication. Quadrature Amplitude Modulation (QAM) is used widely for high data rate communication than BPSK and QPSK, since it carries more bits of information per symbol over the channel. The objective of this work is to minimize the power consumption and area utilization of 32-bit QAM modulator. Methods/Statistical analysis: In this work, three new procedures are introduced for 32QAM modulator. In the first approach, sine and cosine data generated using conventional technique are stored in ROM and the stored data is selected based on the input sequence to generate the output signal. This approach reduces the power consumption and area utilization. In the second approach, information bit stream is modulated with sine and cosine waves generated by iterative algorithm to minimize power and area requirement. In the third approach, booth multiplication algorithm is employed to generate QAM signal. This method of generating QAM signal consumes less power and area in comparison with the conventional modulator. The work is synthesized, analyzed, and compared in 180nm, 90nm and 45nm CMOS technology using Cadence software. Findings: In 180nm CMOS technology power consumption noticed is 60662.740nW, 617020.071nW and 133679.687nW with the proposed method1, method2 and method3 respectively. An Area utilized in 180nm CMOS technology is 1341mm2, 20746.757mm2, and 2754mm2 respectively in proposed 32QAM modulator with ROM, 32QAM modulator with proposed Iterative algorithm and 32QAM modulator with Booth multiplication algorithm. Novelty/Applications: The conventional 32QAM devours additional power and area. In this work area and power reduction is achieved with respect to the conventional method. The same work is carried out with 90nm and 45nm CMOS technology. Three novel approaches to 32QAM are proposed. The proposed work is synthesized, analyzed, tabulated and compared with conventional method and shown that power consumption and area utilization are minimum than compared to the conventional method. Keywords: QAM; multiplier; power; area; communication; cadence

Optimal Design of Ultra-Low-Power 2.4 GHz LNA for IEEE 802.15.4/Bluetooth Applications

In this paper, an evolutionary computation-based optimal design of low power, high gain inductive source degenerated CMOS cascode low noise amplifier (LNA) circuit is presented for 2.4[Formula: see text]GHz frequency. The main challenge for the design of radio frequency (RF) LNAs at nanometer range is the thermal noise generated in the short-channel MOSFETs. The short-channel effects (SCEs), such as velocity saturation and channel-length modulation, are considered for the design of CMOS LNA. The evolutionary algorithm taken for this work is Moth-Flame Optimization (MFO) algorithm. MFO is utilized for the optimization of noise figure (NF) while satisfying all the other design performance parameters like gain, matching parameters at input/output, power dissipation, linearity, stability. Optimal values of the sizes of the transistors and other design parameters in designing the LNA circuit are also obtained from the MFO algorithm. The CMOS LNA circuit is designed by using MFO-based optimal design parameters in CADENCE software with a standard 0.18[Formula: see text][Formula: see text]m CMOS process. The designed LNA shows a gain of 15.28[Formula: see text]dB, NF of 0.376[Formula: see text]dB, the power dissipation of 936[Formula: see text][Formula: see text]W and IIP3 of [Formula: see text][Formula: see text]dBm at 2.4[Formula: see text]GHz. The designed LNA achieves better trade-off which results in an FOM of 42.3[Formula: see text]mW[Formula: see text] and may be useful in the receiver module of IEEE 802.15.4 for WLAN applications.

6 Transistors and 1 Memristor based Memory Cell

Area efficient and stable memory design is one of the most important tasks in designing system on chip. This research concentrates in designing a new type of hybrid memory model by using only nMOS transistors and memristor.<br />The proposed memory cell is very stable during successive read operates and<br />comparatively faster and also occupies less amount of silicon area. The<br />stability of the data during successive read operation and noise margin are in<br />the promising range. Extensive simulation results using LTspice and<br />Cadence software tools demonstrate the validity and competency of the<br />proposed model.

Digitally-Controlled Ring Oscillator for Wide Tuning Range Applications

In this paper, two digitally-controlled ring oscillators (DROs) with similar structure but different constructive cells have been proposed. These proposed DROs include of 5 stages, and each stage contains 10 parallel delay cells. In addition, each stage has fine and coarse parts for adjusting the output frequency. The proposed designs have a wide frequency range and high frequency. The frequency range of the first DRO changes from 1.566 to 20.25 GHz (92.6%) and for the second DRO, its frequency is from 2.218 to 22.86 GHz (90.31%). By considering all possible digital codes for fine and coarse stages, the power consumption of the first DRO changes from 1.1 to 13.64 mW, while this value for the second DRO varies from 144.1 μW to 1.76 mW. The phase noise of the first DRO at the center frequency of 20.25 GHz and the 1 MHz offset is equal to –76.24 dBc/Hz, and at 10 MHz offset the phase noise is equal to –104 dBc/Hz. The phase noise of the second DRO at the center frequency of 22.86 GHz and the 1 MHz offset is equal to –66.64 dBc/Hz, and at the 10 MHz offset the phase noise is equal to –95.39 dBc/Hz. The proposed DROs have been simulated by using the Cadence software in TSMC 65nm CMOS technology and 1.2 V power supply.

Efficient modular hybrid adders and Radix-4 booth multipliers for DSP applications

Adders and multipliers are the fundamental elements of a signal processing architecture. Improve the speed of addition and multiplication operations while minimizing power consumption and area is the problem of interest of this paper. Two versions of modular hybrid adder structures are proposed. The adder structures are derived through the merging of improved carry skip, carry look ahead and ripple carry adder (RCA) concepts. The proposed adder version-1 has improved speed of operation while maintaining power consumption lower than that of RCA. The proposed adder version-2 achieves further improvement in speed through the addition of incrementation scheme at the cost of slight increase in hardware complexity. Two versions of radix-4 booth multipliers are proposed. Among the two versions, the booth multiplier version-1 has the highest speed and lowest power consumption and version-2 has the lowest area compared to most of the existing architectures. Synthesis result show that the delay of proposed multiplier version-1 is reduced by 20.74%, PDP by 45.62% and ADP by 32.26% in comparison with a typical low PDP 8*8 Booth multiplier while consuming 31.4% less power and 14.59% less area. Cadence software with gpdk 45 ​nm standard cell library is used for the design and implementation.