Design of PWM-Based Digital Receiver for 5G

Abstract

The next generation, 5G and 6G standards, are allocated different bands for the same standard due to the worsening shortage of available spectrum. This has led to significant research interest in digitizing the RF signal as close as possible to the antenna motivated by flexibility and high performance allowed by cognitive radio and software defined radio. In this paper, a PWM-based all digital receiver is Presented. A system level simulation of the pulse-width modulator is performed using cadence software. In addition, a high-speed two-stage dynamic CMOS-latched comparator is proposed. In addition, a high-speed ring oscillator for clock generation is given. The proposed pulse-width modulator is implemented with a target technology TSMC 65nm process. The comparator achieves sampling frequency up to 10 GHz with resolution of 10.11 bits and 13.28 bits at 1 GHz sampling clock while keeping the propagation delay less than 64 psec. for 1 mV input voltage difference. Furthermore, the oscillator achieves a 10.025GHz output frequency.