Buried Silicon Dioxide Research Articles

Self-heating effects in SOI bipolar transistors

Self-heating effects in silicon-on-insulator (SOI) bipolar junction transistors (BJT) have been investigated by measurements and electrothermal simulations. The low heat conductivity of the buried silicon dioxide in the SOI material is shown to increase the thermal resistance, leading to thermal runaway effects. The thermal resistance can be decreased and the critical power density for thermal runaway can be increased, by replacing the buried silicon dioxide with another insulator that conducts heat better, e.g., diamond. The thermal resistance at steady-state is shown to decrease with a factor of more than three when using diamond, and considerably more during transient heating.

Novel approaches for low cost fabrication of SOI

Two trials for low cost manufacture of silicon-on-insulator (SOI) wafers were implemented. Low dose separation by implantation of oxygen (SIMOX) procedure has been conducted on a beam-line ion implanter with mass analyzer. The energy dependence of the formed SOI structure was studied at varied implant dosages. The integrity of the buried oxide (BOX) layer was examined by transmission electron microscopy (TEM) and the threading dislocation in the top silicon layer was evaluated by Secco technique. The results indicated that not only the implanted oxygen dose but also the oxygen ion energy plays an important role in the formation of SOI structure with good crystallinity of top silicon, sharp Si/SiO2 interfaces and highly integrated BOX layer free of silicon inclusion. For separation by plasma implantation of oxygen (SPIMOX) approach, water plasma, rather than oxygen plasma, was employed to avoid oxygen spread in the implant depth profile. The SPIMOX process using water plasma was carried out on a beam-line ion implanter without mass selector to simulate the plasma implantation procedure. Cross-sectional TEM study revealed that uniform BOX layer was formed under single crystal silicon superficial layer with the present approach. The interfaces between silicon superficial layer, BOX layer and bulk silicon were smooth and sharp. An implant dose window has been identified for fabricating the desirable SOI structure.

Silicon oxide in SiSi bonded wafers

The properties of surface and buried interface silicon oxide layers in low- and high-temperature SiSi bonded wafers, were investigated using infrared spectroscopy, spectroscopic ellipsometry (SE) and high resolution transmission electron microscopy (HRTEM). Infrared transmission spectra show the absorption by SiOSi vibrations originating from surface and interface silicon oxide. To distinguish the contribution of surface and buried interfaces oxide in the spectra, the surface oxide was removed by chemical etching. The interface oxide thickness was calculated from curve fitting of infrared transmission spectra of the etched bonds. An excellent agreement of values of the interface oxide thicknesses determined using this method with those obtained from HRTEM measurements was found. The behaviour of longitudinal and transversal optical (LO and TO) phonons in surface silicon oxide was analysed. The frequency position of TO and LO modes shifts towards higher energy and the LO-TO splitting decreases upon annealing. This behaviour can be explained in terms of a thermal relaxation model.

Silicon-on-insulator substrates with buried tungsten silicide layer

Tungsten silicide layers can be incorporated into silicon-on-insulator (SOI) substrates produced by direct wafer bonding. The series resistance of collectors/drains in bipolar or smart-power circuits can be reduced to 2 Ω/sq. The out-diffusion of the buried implanted collector contact during the post-bond anneal can be eliminated by using rapid diffusivity of donors and acceptors in tungsten silicide subsequent to bond anneal. Optimisation of this process can provide better matching of vertical complementary bipolar transistors. A novel silicon-on-silicide-on-insulator structure is proposed for integrating p–i–n diodes with low loss coplanar wave-guide lines. This incorporates a polysilicon surface layer on the high resistivity handle wafer and a tungsten silicide back contact to the diode. CPW lines with microwave losses of 2 dB/cm have been obtained at 30 GHz. The incorporation of a tungsten silicide layer below the buried silicon dioxide layer can be used as a ground plane. A tungsten silicide ground plane used with a standard SOI test structures was found to increase the suppression of cross-talk by 20 dB in the frequency range 1–10 GHz. Other potential applications such as ground plane and double-gate MOSFETs are discussed.

Growth of buried silicon oxide in Si–Si bonded wafers upon annealing

Properties of the buried silicon oxide layer in Si–Si bonded wafers upon annealing were studied using Infrared (IR) spectroscopy and high resolution transmission electron microscopy (HRTEM). IR spectra of chemically etched Si–Si bonded wafers allow the thickness of the buried oxide layers to be evaluated. The increasing thickness of the buried oxide layer with annealing temperature is determined via a curve fitting procedure of IR spectra measured in the spectral range of longitudinal optical and transversal optical phonons in silicon oxide. The behavior observed is in very good agreement with that obtained from HRTEM measurements.

Optimized technology for the fabrication of piezoresistive pressuresensors

In this work a technology for the fabrication of piezoresistivepressure sensors is presented, based on the use of silicon BESOI (bondedand etch-back silicon on insulator) wafers. The main purpose of theproposed technology is the optimization of the thin silicon diaphragmdefinition process that is one of the most critical steps in thefabrication of silicon pressure sensors. The buried silicon oxide layer ofthe BESOI wafers is used as an automatic etch stop of the siliconanisotropic etching, making it possible to obtain very precise control ofthe sensor diaphragm thickness. In addition, the type and thickness of thelayers acting as masking materials on the backside of the wafers have beenoptimized in order to get a high-yield process. The experimental resultsobtained when using the proposed technology are presented and discussed.

Synthesis of buried silicon oxide layers by water plasma immersion implantation

Buried silicon oxide layers were produced by water plasma immersion oxygen ion implantation and investigated by transmission electron microscopy, optical emission spectrometry, elastic recoil-detection analysis and Rutherford backscattering. Especially H 2O +-ions, but also HO +-, O 2 +- and O +-ions, were implanted into silicon by pulse biasing the silicon wafer to a voltage between −40 and −50 kV. The pulse duration was 15 μs, the repetition rate was 200 Hz and the pulse number was varied between 0.92 × 10 5 and 29.5 × 10 5 pulses. The temperature during implantation was between 420°C and 800°C. The subsequent annealing process at 1250°C for 5 h leads to buried silicon oxide layers with smooth interfaces. The shape of the oxygen concentration profiles is caused by superposition of the low-energy O +-ion and the high-energy H 2O +- and HO +-ion profiles. The thickness of the damaged regions and the hydrogen contents decrease with increasing temperature. The application of water plasma has the advantage that the ion range is about twice the given ion energy because ionized oxygen atoms are implanted.

Silicon-based resonant-cavity-enchanced photodiode with a buried SiO2 reflector

We report on a silicon-based resonant cavity photodiode with a buried silicon dioxide layer as the bottom reflector. The buried oxide is created by using a separation by implantation of oxygen technique. The device shows large Fabry–Pérot oscillations. Resonant peaks and antiresonant troughs are observed as a function of the wavelength, with a peak responsivity of about 50 mA/W at 650 and 709 nm. The leakage current density is 85 pA/mm2 at −5 V, and the average zero-bias capacitance is 12 pF/mm2. We also demonstrate that the buried oxide prevents carriers generated deep within the substrate from reaching the top contacts, thus removing any slow carrier diffusion tail from the impulse response.

Short-timescale thermal mapping of semiconductor devices

We report spatial mapping of temperature fields in semiconductor devices with sub-microsecond temporal resolution. The measurements are performed at a facility that integrates scanning laser-reflectance thermometry with electrical stressing capability. Data for SOI LDMOS transistors investigate transient heat diffusion within the buried silicon dioxide and capture large temperature gradients in the drift region, which result from the spatially-varying impurity concentration. The new thermometry facility is promising for the study of transistor and interconnect thermal failure due to electrostatic discharge (ESD).

MBE growth and characterization of buried silicon oxide films on Si(100)

Silicon molecular beam epitaxy (Si-MBE) has been used to produce silicon oxide (SiO x ) films by evaporating Si on a heated Si(100) substrate in an ultra high vacuum system with an O 2 pressure of 10 −6 to 10 −4 mbar. Then the SiO x films were overgrown with pure Si. The influence of the substrate temperature, the O 2 pressure and the Si deposition rate on the oxygen content in the SiO x films and on the crystalline quality of the Si top-layer was investigated by Rutherford backscattering spectrometry and ion channeling. Epitaxial growth of the Si top-layer was observed up to a maximum concentration of ≈20 at.% oxygen content in the SiO x film. Cross-sectional transmission electron microscopy shows that the structure of the SiO x film changes duringa subsequent annealing procedure. Electron energy loss spectrometry proves that amorphous SiO 2 is formed and the development of holes indicates that the density of the as-grown SiO x film is much lower than that of SiO 2. The specific for the as-grown SiO x films was determined by I– V measurements.

A model for SIMOX buried-oxide high-field conduction

A new model for SIMOX buried-oxide (BOX) high-field conduction which incorporates the role of silicon islands and BOX nonstoichiometry is presented. For single-implant SIMOX BOX high-field conduction, the onset E-field for both positive and negative applied bias is much lower than the expected onset E-field for that of thermal oxide. In addition, the onset E-field for injection from the substrate is lower than for injection from the top-silicon. We propose that conduction by electron injection from the top interface is due to Fowler-Nordheim tunneling with oxide nonstoichiometry induced modification of the effective barrier-height. Conduction by electron injection from the bottom interface is due to a two-step Fowler-Nordheim tunneling mechanism with cathode E-field enhancement caused by the presence of silicon islands located near the oxide-substrate interface of single-implant SIMOX. These mechanisms were verified using numerical simulation, electrical, and physical measurements. A modified Fowler-Nordheim equation can be used to model BOX conduction through the addition of three parameters, k/sub e/, k/sub a/, and o/sub BOX/. The E-field enhancement factors (k/sub e/ and k,/sub a/) can be directly correlated to silicon island shape, location and density, while the effective barrier-height (o/sub BOX/) can be correlated to BOX nonstoichiometry. Monitoring these parameters has potential use as a simple method for SIMOX BOX quality control.

Formation of buried oxide in silicon using separation by plasma implantation of oxygen

Plasma immersion ion implantation (PIII) is used to fabricate buried oxide layers in silicon. This ‘‘separation by plasma implantation of oxygen’’ (SPIMOX) technique can achieve a nominal oxygen atom dose of 2×1017 cm−2 in implantation time of about 3 min. SPIMOX is thus presented as a practical high-throughput process for manufacturing silicon-on-insulator. In the SPIMOX samples prepared, three distinct modes of buried oxide microstructure formation are identified and related to the as-implanted oxygen profiles. A first-order model based on oxygen transport and oxide precipitation explains the formation mechanisms of these three types of SPIMOX layers.

Transient Measurements of Heat Distribution in Devices Fabricated on Silicon-On-Diamond Material

Thermal properties of devices fabricated on different silicon-on-diamond (SOD) and silicon-on-insulator (SOI) structures have been investigated. A new method for transient measurements of temperature distributions in the SOI/SOD materials has been developed and demonstrated. The heat is detected as a shift in avalanche voltage in p-n diodes fabricated on these materials. Devices on diamond/copper were found to be more than two times cooler than devices on oxide/silicon structures. The measured results were also compared with results from computer simulations in order to estimate the thermal coefficients of the silicon device layer, the buried silicon dioxide, and the diamond material. The thermal conductivity of the polycrystalline diamond film in this work was estimated to be 2 W·cm-1·K-1, which is about 140 times higher than the value of the buried silicon dioxide layer.

Nondestructive characterization of SIMOX structures

In this paper we show how the technique of microscope-spectrophotometry (MSP) may be used to characterize SIMOX structures nondestructively. A range of SIMOX materials prepared using various implantation conditions were investigated. The structural parameters elucidated using MSP included: silicon overlayer and buried oxide thicknesses; approximate densities of silicon islands in the buried oxide layer and silicon dioxide islands in the silicon overlayer as appropriate. These results compared favourably with those obtained using XTEM and indicates that MSP is a reliable technique for the nondestructive, three dimensional characterization of complex multi-layer structures. Furthermore, the technique is capable of examining very small areas (1 μm) which should enable device structures and local inhomogeneities to be characterized.

Breakdown mechanism in buried silicon oxide films

Charge injection leading to catastrophic breakdown has been used to study the dielectric properties of the buried oxide layer in silicon implanted with high-energy oxygen ions. Current versus gate bias, current versus time, and capacitance versus gate bias were used to characterize, at various temperatures, MOS metal-oxide-semiconductor capacitors with areas in the 1×10−4–1×10−2 cm2 range fabricated with commercially available single- or triple-implant separation by implanted oxygen silicon wafers. The data show that injected charge accumulates in the buried oxide at donorlike oxide traps ultimately leading to catastrophic breakdown. Both Poole–Frenkel and Fowler–Nordheim conduction, as well as impact-ionization mechanisms, have been identified in the oxide. The charge and field to breakdown in the best buried oxides are, respectively, near 1 C cm−2 and 10 MV cm−1, similar to the thermally grown oxide parameters. Cumulative distributions of these parameters measured over a large number of capacitors show that the frequency of breakdown events caused by extrinsic defects is scaled with the capacitor area. Intrinsic and extrinsic defect distributions are broader than with thermally grown oxides.

Thin buried oxide in oxygen-implanted silicon

SiO 2 precipitation in oxygen-supersaturated silicon was studied. Oxygen was inserted by ion implantation into single-crystal silicon. Evidence is given for a special phenomenon of oxygen blocking due to hot clouds resulting from collisional cascades. In the region where blocking is active, precipitates are formed in as-implanted conditions. A model is formulated and specialized to predict the dependence on depth of precipitate density and size. The existence of a buried region of precipitates is useful for producing a thin buried oxide. The L ow- D ose SIM OX (LODOX) structure obtained provides a solution for many problems that are typical of silicon substrates for CMOS applications.

Electron-probe microanalysis of silicon implanted with oxygen and nitrogen

High dose ion implantation is a promising technique to form a silicon-on-insulator material. Possible ions for implantation are oxygen and nitrogen, to form insulating layers of buried silicon-oxide and silicon-nitride, or a combination of oxygen and nitrogen, to form silicon oxynitride.One of the problems in analyzing the results of an ion implantation is that it is hard to establish the depth-distribution of the implanted ions in a straight-forward way. Several techniques are available; each of them with their own advantages and disadvantages. A promising approach might be in-depth profiling with the electron probe microanalyzer.The first step in this analysis method is to accurately measure the k-ratios of all the elements involved at a range of accelerating voltages, starting at as low a voltage as possible.The second step is to analyze these measurements with a sophisticated multi-layer analysis (MLA) program. In our laboratory we use an MLA program based on our "PROZA"-bulk correction program, of which we previously explained how it can be expanded to a thin film analysis program.

Modelling of the formation of buried dielectric layers by ion implantation

The formation of buried silicon dioxide or nitride layers by high-dose implantation (typically 1018 ions cm2) of energetic ions at elevated target temperatures is being extensively studied to produce silicon-on-insulator structures for device applications. The present paper reviews the different approaches to model these processes. The phenomenological models reported so far describe the modification of ion range profiles by target swelling, changing target composition, surface sputtering, and diffusion of unbonded implanted species. Reasonable oxygen or nitrogen depth profiles can be computed, but the electrically active microstructures in the synthesized layer systems are still beyond the scope of these simulations.

Effect of microscale thermal conduction on the packing limit of silicon-on-insulator electronic devices

Silicon-on-insulator (SOI) electronic circuits have a buried silicon dioxide layer which inhibits device cooling and reduces the thermal packing limit, the largest number of devices per unit substrate area for which the device operating temperature is acceptably low. Thermal analysis yields the packing limit of SOI MOSFET devices in terms of the targeted channel-to-substrate thermal conductance. Thermal conduction is microscale if it is significantly reduced by the boundary scattering of heat carriers, phonons in silicon and electrons in aluminum. Microscale effects are negligible above room temperature, but may reduce the packing limit by 44% for a substrate temperature of 77 K.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Characterization of oxygen-ion-implanted silicon using spectroscopic ellipsometry and transmission electron microscopy

Separation by implanted oxygen (SIMOX) substrates from several research production processes including low energy implantation, multiple implantation and low dose studies were characterized using spectroscopic ellipsometry, cross-sectional transmission electron microscopy (XTEM) and planar view TEM. Silicon and buried silicon dioxide layer thicknesses determined by spectroscopic ellipsometry are shown to be within 2% and 8% of the XTEM measurements respectively. Experimental results indicate that it is doubtful whether a direct correlation can be established between a crystalline quality parameter in the superficial silicon layer, as extracted from spectroscopic ellipsometry data via an effective medium approximation, and the defect density as determined by planar view TEM. These results indicate that the development of a more sophisticated dielectric response model is necessary to mirror accurately the complexity of this microstructure.