Bump Metallurgy Research Articles

Reliability Analysis of Flip-Chip Packaging GaN Chip with Nano-Silver Solder BUMP.

Gallium nitride (GaN) power devices have many benefits, including high power density, small footprint, high operating voltage, and excellent power gain capability. However, in contrast to silicon carbide (SiC), its performance and reliability can be negatively impacted by its low thermal conductivity, which can cause overheating. Hence, it is necessary to provide a reliable and workable thermal management model. In this paper, a model of a flip-chip packing (FCP) GaN chip was established, and it was assigned to the Ag sinter paste structure. The different solder bumps and under bump metallurgy (UBM) were considered. The results indicated that the FCP GaN chip with underfill was a promising method because it not only reduced the size of the package model but also reduced thermal stress. When the chip was in operation, the thermal stress was about 79 MPa, only 38.77% of the Ag sinter paste structure, lower than any of the GaN chip packaging methods currently in use. Moreover, the thermal condition of the module often has little to do with the material of the UBM. Additionally, nano-silver was found to be the most suitable bump material for FCP GaN chip. Temperature shock experiments were also conducted with different UBM materials when nano-silver was used as bump. It was found that Al as UBM is a more reliable option.

Fabrication and Mechanical Properties Improvement of Micro Bumps for High-Resolution Micro-LED Display Application

Recently, many significant strides have been made for the integration of micro-light-emitting diodes (Micro-LEDs) in display. However, the reflow process is usually accomplished under formic acid or hydrogen ambient, which is irritating, flammable, explosive, and very expensive. For reliable micro bumps in the flip-chip package, it is essential that the correlations among mechanical properties, fracture mechanisms, and interfacial reactions of micro bumps formed on a silicon substrate be understood. In this article, a novel under bump metallurgy (UBM) structure based on SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> openings was described, as a result of which the indium micro bump arrays with a pitch of 40 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> and a diameter of 15 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> were successfully fabricated by the reflow process via glycerol. The effect of reflow time and reflow temperature on the reliability of indium micro bumps was also investigated. Experimental results showed that the average shear strength of indium micro bumps peaked at the reflow conditions of 200 °C for 180 s and decreased with further increasing reflow time and temperature. It was considered that the stable AuIn <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> intermetallic compounds (IMCs) formed toward the solder joint improved the shear strength after reflowed at 200 °C for 180 s. As the reflow time and temperature increased, the grain size of IMCs increased, which weakened the interfacial connection. In addition, the transfer and bonding reliability of Micro-LED chips through the flip-chip bonding process have also been discussed.

An Investigation into Thermomigration Failure of Flip Chip Solder Joint Interconnects used in High Reliability Applications

Abstract The experimental study described herein investigates thermomigration of both eutectic Sn/Pb and lead free Sn/Ag/Cu solder joints, with the additional focus on the development of an Arrhenius failure model of time-to- failure as a function of temperature. Flip chip test vehicles were assembled with daisy chain die, with and without underfill, attached to ceramic and organic package substrates, using standard reflow processes. Three different under bump metallurgy technologies were investigated: sputtered thin film Al/NiV/Cu, thick electroplated nickel, and thick electroplated copper (i.e., copper pillars). The test vehicles were subjected to unbiased high temperature storage (HTS) testing with temperatures ranging from 125°C to 200°C. Failure was determined from continuity testing at regular intervals until an open circuit or high resistivity was detected. The results demonstrate the robustness of Al/NiV/Cu UBM at temperatures less than 130°C, and of the thick electroplated UBM at temperatures of 150°C. Based on the HTS test results, and corresponding analyses, a thermomigration failure model was generated for eutectic Sn/Pb and lead free Sn/Ag/Cu solder alloys using an Arrhenius-like fit to the failure data.

A new spalling mechanism of intermetallics from the adhesion layer in the terminal-stage reaction between Cu and Sn

Three-dimensional integrated circuits provide a promising approach to extend Moore's law by vertically stacking multiple functional chips with microbumps. However, with miniaturization, depletion of the wetting layer of under bump metallurgy becomes a worrisome possibility. Upon depletion of the wetting layer, the adhesion layer will be directly exposed to intermetallics at the terminal stage of solid-state reactions. In this study, the resulting spalling phenomenon is investigated for the first time. The microstructure evolution of ultrathin Cu–Sn microbumps shows that spalling of Cu6Sn5 and Cu3Sn from the Cr adhesion layer occurs when Cu is depleted. The driving force for spalling is the high interfacial energy between intermetallics and the Cr adhesion layer. To prevent such spalling, which deteriorates the integrity of the bumps, the Cu wetting layer must be at least 1.3 times thicker than that of Sn.

Pulse Electroplating of Ni-W Alloy for the Diffusion Barrier in Under Bump Metallurgy.

Ni-W alloy was electroplated from citrate bath. The crack-free coatings were obtained using the pulse electroplating method. The surface hardness was increased up to 700 Hv and it is twice as high than that of the electroplated Ni. The surface hardness was increased as the content of W in the coating increased. However, the higher W contents made surface cracks and the surface hardness was decreased. Ni-W alloy made less intermetallic components (IMC) and the shear force of solder ball was increased as much as 20% compared with conventional Ni plating.

Electromagnetic Interference Shielding from the Back-Side Metallization of the Chip in Fan-Out Wafer Level Package

Shielding against electromagnetic interference (EMI) is becoming increasingly important as electronics such as wearable devices, sensors, IoT, and smartphones become smaller, faster, and weigh less. Package level EMI shielding has several advantages over board level shielding, such as a higher packaging density and better design flexibility. We developed a new fan-out package structure using back-side under bump metallurgy (UBM) and a substrate (or metal carrier) to improve the thermal characteristics and reduce die shift. UBM and the substrate (or metal carrier), which consisted of highly conductive metals, is effective for EMI shielding. We study EMI shielding effects of UBM and the substrate (or metal carrier). To determine the EMI shielding of the UBM structures, Ti (17 nm thick) and Cu (70 nm thick) were sequentially deposited on a glass substrate using a direct-current (DC) magnetron sputtering system. Then Cu was electroplated or Ni-P was electroless plated with various thicknesses up to 10 µm. Samples were measured under 100 MHz and 1 GHz with 0 dB conditions using a spectra analyzer, which is a near-field measurement equipment. In unpatterened UBM, increase in the Cu or Ni thickness resulted in further enhanced EMI shielding. When the thickness of Cu UBM or Ni-P UBM was bigger than 5 µm or 3 µm, respectively, the UBM exhibited good EMI shielding. A double layer of Cu strips was formed on the back side of the chip to enhance EMI shielding. The larger the overlap between the Cu strip and the upper and lower layers, the better the EMI shielding effect. When this overlap was larger than 0.5 mm, the EMI SE was similar to that of a single unpatterned Cu layer. We demonstrated good EMI shielding in the double-layered structure with a large overlap width between the upper and lower Cu strips, and expect better moisture release in such structures.

Panel-Level Chip-Scale Package With Multiple Diced Wafers

In this study, a very high-throughput and low-cost packaging method for fabricating the fan-in chip-scale package is presented. Emphasis is placed on the utilization of the existing printed circuit board (PCB) panel carriers and the corresponding PCB equipment for making the redistribution-layers (RDLs), vias, under bump metallurgy (UBM), contact pads, solder mask, and surface finishing of the package. Since all the PCB panels are in rectangular shape, some of the device wafers are diced into two or more pieces so the panel is fully utilized.

Electrical, Thermal, and Mechanical Characterization of eWLB, Fully Molded Fan-Out Package, and Fan-Out Chip Last Package

Fan-out (FO) packages are widely used in handheld, mobile consumer, and Internet of Things (IoT) devices due to the facility they provide for a greater I/O density and the integration of multiple components in a single package. Various types of FO package are available, including embedded wafer-level BGA (eWLB), fully molded (FM), and a flip-chip-based structure referred to as a fan-out chip-last package (FOCLP). In this paper, ANSYS simulations are performed to examine the warpage, extreme low- $k$ (ELK) interconnect stress and board-level solder joint reliability of the various package types. The validity of the simulation model is confirmed by comparing the numerical results for the warpage of the eWLB and FM packages with the experimental observations. Further simulations are then performed to investigate the heat dissipation performance and electrical crosstalk properties of the three packages. Taguchi experiments are conducted to examine the effects of eight control factors [namely, the inclusion (or otherwise) of a backside laminate film, the board thickness, the joint standoff distance, the ball joint diameter, the under bump metallurgy (UBM) diameter, the joint pitch, the die thickness, and the Cu pillar height] on the thermomechanical reliability of the FM package under accelerated thermal cycling testing. Finally, the Taguchi analysis results are used to determine the optimal geometry design of the FM package.

P‐6.4: Failure Analysis of Al Corrosion Issue at Complementary Metal Oxide Semiconductor Backplane Solder Process for 1980PPI Micro Light Emitting Diode Display

Micro light emitting diode (LED) display fabricated on complementary metal oxide semiconductor (CMOS) backplane provide smaller size, higher contrast ratio and energy efficiency, can be accommodated to market applications such as augmented reality (AR)/virtual reality (VR). Hybridization of compound semiconductor Micro‐LED arrays with CMOS active matrix driver integrated circuit (IC) using flip‐chip technology is major solutions proposed, in which under bump metallurgy (UBM) and solder process is fabricated on CMOS backplane and followed by flip‐chip process with LED chips. In our experiment, AL corrosion issue at CMOS top metal electrode in UBM and solder process occurred during 1980PPI micro display fabrication. After scanning electron microscope (SEM) &amp; focused ion beam (FIB) analysis, it's suspected that uneven passivation sidewall profile and poor bottom coverage of UBM metal at passivation sidewall induced developer liquid in following PR remove step penetrating to AL electrode surface and corrode it. Passivation etching recipe modification and UBM metal bottom coverage improvement could solve this issue

Study of Electrodeposited High Entropy Single Element (HESE) Cu for Cu-Cu Direct Bonding

Electronic industry had required the smaller size and the higher performance of the device. According to Moore’s law, Technology node which also represents minimum feature size have shrank as rate of 0.7 and density of semiconductor have doubled about every two years. However, decreasing of technology node have been confronted with limit to more dense packaging by two-dimensional large-scale integrated circuits (ICs). Therefore, it is essential that developing of packaging techniques from two-dimensional ICs to three-dimensional ICs. The critical essentials of three-dimensional die stacking technology are TSV (through silicon via) and micro-bump. These technologies have contributed to the appearance of HBM (high bandwidth memory). HBM was packet of the memory, which composed of several stacked layers of the memory chips. Each memory chips were vertically connected by TSV and micro-bump. Thus, HBM have lower RC delay and higher performance of data processing than two-dimensional packaged memory. Even though advance of memory packaging have progressed, the lower pitch size and the higher density of memory chips have been requested ceaselessly in electronics packaging industry. Because the requiring of HPC (high performance computing) in the IT industry field such as AI (artificial intelligence), IOT (internet of things) and VR (virtual reality) have maintained. Especially, in order to accomplish vertical fine height between memory chips in the fine pitch packaging of HBM, micro-bump which consists of copper pillar, deposition of nickel diffusion barrier, and tin-silver or tin-silver-copper based cap have been used. TCB (thermal compression bonding) and reflow process (thermal aging) are typical fabrication process of micro-bump in HBM to combine between tin-silver or tin-silver-copper caps in the temperature range of 200 to 300 degree Celsius. However, there would be issues of reliability of micro-bump in fine-pitch bonding since intermetallic compound (IMC) formed through the reaction between under bump metallurgy and bump cap at smaller area due to lower pitch. For example, during reaction, if atomic flux difference between top and bottom occurred, kirkendall void which provides track of brittle fracture at IMC layer after reflow process could be formed. Moreover, during reflow, if side wetting of tin atoms from solder occurred, solder depletion can be appeared. Solder depletion also cause a serious issue of reliability of micro-bump. In order to remove these problems and make smaller interconnect, bump cap-less interconnect has been considered. Among many ideas related to bump cap-less interconnect, copper-to-copper direct bonding between copper pillar have been considered due to stability for electromigration, low resistivity and not utilizing IMC. However, more heat energy needs to trigger diffusion. [1] In this study, to decrease the challenges of bump bonding process, copper-to-copper direct bonding was conducted below 300℃. For triggering diffusion between copper below 300℃, high entropy single element (HESE) Cu film have been used. HESE Cu film is electrodeposited film which is reinforced self-annealing property. And HESE Cu films have been fabricated by electrochemical process at condition of low temperature and high current density. The self-annealing property of HESE Cu film arose from high defect density and non-equilibrium grain boundaries at the triple junction. The copper-copper bonding experiments were performed using thermal pressing machine. Thermal parameters and pressure parameters were varied to obtain proper bonded samples. The HESE Cu films were characterized by SEM (scanning electron microscope) and EBSD (Electron backscattering diffraction). The microstructure of HESE Cu films were examined by TEM (transmission electron microscopy). Chen, Chih, Doug Yu, and Kuan-Neng Chen. "Vertical interconnects of microbumps in 3D integration." MRS Bulletin40.3 (2015): 257-263.

Signal Integrity Design and Analysis of Silicon Interposer for GPU-Memory Channels in High-Bandwidth Memory Interface

In this paper, for the first time, we designed and analyzed channels between a graphic processing unit and memory in a silicon interposer for a 3-D stacked high bandwidth memory (HBM). We thoroughly analyzed and verified the electrical characteristics of the silicon interposer considering various design parameters, such as the channel width and space, redistribution layer via, and under bump metallurgy pads. In particular, we also considered the meshed ground planes used for the proposed transmission lines, which are microstrip and strip lines. Signal integrity (SI) of the proposed channels in the silicon interposer was successfully analyzed and verified using a full 3-D electromagnetic solver and circuit simulations. Based on the extracted lumped circuit resistance, inductance, conductance and capacitance parameters, we thoroughly analyzed the channel characteristics and identified the parameters that dominantly affect SI in relation to each frequency range. From the analyzed insertion loss and far end crosstalk, we verified SI of the silicon interposer by eye-diagram simulations in terms of eye-height voltage and timing jitter in the time domain. In the worst case, the eye-height voltage and timing jitter of the proposed microstrip lines are 0.911 V and 36.8 ps, respectively, with 72 mV of signal coupling. The eye-height voltage and timing jitter of the proposed strip line are 0.887 V and 42.1 ps with 34 mV of single couplings. We show that the proposed channels of the silicon interposer can successfully transfer data at a 2-Gb/s data rate. Finally, we propose concepts and solutions for the next-generation HBM interface with higher data rates up to 8 Gb/s.

Electroless Under Bump Metallurgy Deposition on Batches of Singulated Semiconductor Die

Multi project-wafers (MPWs) offer cost-effective options for fabrication of application specific integrated circuits (ASICs) produced for entities not requiring a large volume of die from a dedicated full wafer run at an advanced semiconductor foundry. MPWs consist of a mixture of different devices shared on a single wafer; thereby reducing cost of processing by allowing the purchase of real estate allotted to each device. This practice is advantageous for those in academia or government that often only require small quantities of devices for research or niche applications. With many teams investing in a single wafer run, strict design rules must be followed on these microelectronic chips. In particular, the metal used in the final routing layer must be AlCu. This AlCu metallization is not compatible with solder connections for flip chip bonding applications because solder is unable to wet AlCu. To allow MPW die integration with flip chip bonding applications, a solder compatible under bump metallization (UBM) must be deposited on top of the AlCu. This UBM deposition can be achieved through physical vapor deposition and subsequent electrolytic plating into a photolithography defined plating mold. Unfortunately, photolithographic processes are only compatible with full wafers and not with singulated die. This leaves electroless deposition methods such as immersion tin or zinc followed by electroless nickel, electroless palladium, immersion gold (ENEPIG) or electroless nickel and immersion gold (ENIG) as the only options for depositing a wettable UBM on MPW die. Electroless deposition can be performed with a single die at a time, however this process is not well suited for manufacturing. In this work, we have developed a scheme for batch level UBM deposition on singulated semiconductor die by coupling temporary bonding with electroless deposition. A unique batch approach is proposed to electrolessly deposit UBM to terminal AlCu on MPW die. Preliminary Si sidewall passivation is used to eliminate metallization of unintended surfaces in subsequent steps. Temporary custom fixturing onto a carrier substrate is leveraged allowing a variety of devices to be processed like a full wafer, establishing feasibility for industrial scaling. The bulk aluminum oxide is then solubilized by chemical etching and replaced by reduction of Sn as a base layer for ENIG and ENEPIG processes as seen in Figure 1. After metal deposition, devices are liberated from the temporary mounting substrate making them ready for flip chip bonding. Due to creating an UBM through electroless processes, options for interposer bumps are limited and outlined in Figure 2. Solder bonds from Cu pillars topped with SnAg or electroplated with either AuSn or SnAg allow a reflow solder attachment to complete electrical contact between the two chips. Electroplated Au bumps allow for a thermocompression bond to be made between the two chips. Both methods have benefits based on circumstance. Reflow solder is advantageous for fragile chips that cannot withstand the high pressure associated with thermocompression. Cu pillars are also attractive for RF devices in that Cu offers reduced electrical parisitics. Thermocompression is advantageous because it does not require high level of uniformity in the final Au bump. In this presentation, we will provide details on the passivation, batch level handling process, uniformity, and yield statistics for the electroless deposition. Supported by the Laboratory Directed Research and Development program at Sandia National Laboratories, a multimission laboratory managed and operated by National Technology and Engineering Solutions of Sandia, LLC., a wholly owned subsidiary of Honeywell International, Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA-0003525. Figure 1

Process enabling highly accurate die position for fan‐out package applications

A new process that can improve die shift issue in process utilising back-sided under bump metallurgy (UBM) via a self-alignment effect for fan-out package applications is proposed. The die and the pad of the substrate are spontaneously aligned and the degree of accuracy is very high after reflow. For the experiment, two kinds of UBM pads were prepared on glass dies and the SAC305 solder was formed on the copper pads of an frame retardent (FR)-based substrate. The die shift value was from 20 to 50 μm after pick-and-placement. After reflow, the maximum die shift value was <1 μm. An initially misaligned die with a large shift was aligned with a high degree of accuracy during reflow due to the surface tension of the molten solder. The proposed process improves the die shift issue in the fabrication of fan-out wafer-level packaging and the active die embedded substrate.

In brief

PAGE 800 A relaxation oscillator with no comparator and no reference voltage is presented in work from China. By replacing a conventional comparator with a pseudo-inverter chain it avoids comparator offset effect, achieving low temperature coefficient and ultra-low power consumption. The resulting fully-integrated relaxation oscillator is aimed at energy harvesting applications requiring ultra-low power consumption. PAGE 789 Researchers in China present a terahertz transmit array made using PCB technology. Their proposed approach is low-cost with simple structures and they expect it to reduce the overall cost of THz systems. The device they have demonstrated provides 360° phase coverage with a transmission coefficient better than −3.52 dB at 250 GHz. The oscillator is designed to achieve ultra-low power consumption for use in energy harvesting systems PAGE 797 A team in Japan have developed a vertically-tapered spot-size converter (VT-SSC) using a simpler fabrication process than previously reported InP-based SSCs. The VT core layer was formed by dry etching using the micro-loading effect and the resulting device is very compact at just 200 µm. The team say the compactness and easy fabrication of the VT-SSC mean it can be used to improve the optical coupling loss that occurs during InP photonic integrated circuit assembly. Low-cost PCB techniques were used to manufacture the terahertz transmit array PAGE 814 Work from the UK explores the possibilities of using social media data to map service blackspots in cellular networks. In the example presented, natural language processing techniques have been applied to twitter posts to identify quality of experience complaints and this is combined with the geo-tagging data to identify blackspots and present small-cell deployment recommendations. The simpler manufacture and compact form of the converter will help reduce optical losses incurred during circuit assembly PAGE 810 Researchers in Korea have developed a process that allows dies to align spontaneously on a pad of substrate without the use of die-attach equipment. Their new process uses the under bump metallurgy (UBM) on the back of the chips to improve the die shift issue for fan-out wafer-level packaging, reducing maximum die shift to less than 1 µm. They believe this approach could also be applied to panel-level fan-out packages. Natural language processing of tweets is used to identify quality of experience complaints in mobile networks and map service blackspots The new approach uses UBM on the reverse of the chip to reduce die shift during manufacture

Comparative study on the wettability and interfacial structure in Sn–xZn/Cu and Sn/Cu–xZn system

Zn is the common used alloying element in Pb-free solder to depress the growth of interfacial intermetallic compound (IMC) in solder joints, but is also an oxidation preferred element to decrease the wettability of solder. This paper provides a potential replacement on the Zn-contained solder with small amount of Zn alloyed Cu substrate to avoid the deterioration on wettability but keep the depressing effect on growth of IMC through the comparative study on Sn–xZn/Cu and Sn/Cu–xZn. To systematically study the effect of Zn alloying, 0.2–0.8 wt% content of Zn was added into pure Sn solder and 2.29 and 4.89 wt% content of Zn was alloyed into Cu substrate. The wettability, interfacial reaction during soldering and interfacial IMC growth of Sn–xZn/Cu and Sn/Cu–xZn during isothermal aging were studied and compared with Sn/Cu system. Zn alloyed into Cu substrate exhibited a far better wettability than Zn alloyed into solder. Although there was no significant change on the composition, morphology and thickness of interfacial of IMC in Zn-contained system during soldering, Zn alloyed into Cu substrate or Sn solder obviously depressed the formation of Cu3Sn and the growth of IMC layers during isothermal aging compared with Sn/Cu system. The depressing effect and calculated activation energy on the growth of IMC increased with the content of Zn in Cu or in Sn, and can be attributed to the CuZn solid solution existed at the interface because it decreased the driving force on formation of Cu3Sn and the diffusion rate of Cu atoms. Compared Sn/Cu–xZn with Sn–xZn/Cu, Cu–4.89Zn substrate provided a similar depressing effect on IMC growth but an exceeding wettability compared with Sn–Zn solder, and can be offered as an alternative under bump metallurgy (UBM) in solder joints.

Al 및 SiN 박막 위에 형성된 TiW Under Bump Metallurgy의 스퍼터링 조건에 따른 Au Bump의 접착력 특성

Al 및 SiN 박막 위에 형성된 TiW Under Bump Metallurgy의 스퍼터링 조건에 따른 Au Bump의 접착력 특성

Formation of solid-solution Cu-to-Cu joints using Ga solder and Pt under bump metallurgy for three-dimensional integrated circuits

Three-dimensional (3D) integrated circuits (ICs) are the most important packaging technology for next-generation semiconductors. Cu-to-Cu throughsilicon via interconnections with micro-bumps are key components in the fabrication of 3D ICs. However, significant reliability concerns have been raised due to the formation of brittle intermetallic compounds in the entire 3D IC joints. This study proposes a Ga-based Cu-to-Cu bonding technology with Pt under bump metallurgy (UBM). A systematic analysis of reactive wetting between Ga solders and polycrystalline, single-crystalline, and Ptcoated Cu substrates was conducted. Pt UBM as a wetting layer was identified to be a key component for Ga-based Cu-to-Cu bonding. Pt-coated Cu substrates were bonded using Ga solders with various Ga-to-Pt ratios (n) at 300℃. When n ≥ 4, the Cu/Pt/Ga/Pt/Cu interface evolves to Cu/facecentered cubic (fcc)/γ1-Cu9Ga4/fcc/Cu, Cu/fcc/γ1-Cu9Ga4 + Ga7Pt3/fcc/Cu, and finally Cu/fcc + Ga7Pt3/Cu structures. The desired ductile solid solution joint formed with discrete Ga7Pt3 precipitates. When n ≤ 1, a Cu/Ga7Pt3/Cu joint formed without Cu actively participating in the reactions. The reaction mechanism and microstructure evolution were elaborated with the aid of CALPHAD thermodynamic modeling.

Effects of Under Bump Metallurgy (UBM) Materials on the Corrosion of Electroless Nickel Films

The “black pad” phenomenon, which refers to the blackening of electroless-plated nickel–phosphorus [Ni(P)] films during the immersion Au process, is reproduced using pure chemicals and its fundamental mechanisms are investigated. In the present analysis, under bump metallurgy (UBM) materials have profound effects on the black pad susceptibility, and the presence of abnormally large nodules (ALNs) is essential to the black pad occurrence. The Ni(P) films over Cu, Ag, and Au substrates all exhibit ALNs and are susceptible to black pads, while those over Ni and Co substrates do not have ALNs and therefore are not susceptible to black pad. In the former cases, submicron scale nodular variations of the surface curvature lead to variations in the P concentration in the Ni(P) films, which induces sufficiently large potential differences to drive galvanic corrosion when exposed to the electrolyte, which is a gold cyanide solution in this study. The UBM effect is ascribed to differences in the Ni(P) film growth mode, where the transition from a layer-by-layer growth mode to an island growth mode is easier over Cu, Ag, and Au UBMs.

Solid-state reactions between Sn-20.0 wt.%In-x wt.%Zn solders and Ag and Ni substrates

The Sn-20 wt.%In (Sn–20In) alloy is a promising base material for low-temperature Pb-free solders. Zn is usually added in solders to reduce the extent of undercooling during reflow, while Ag and Ni are commonly seen under bump metallurgy in contact with solder in electronic products. In this study, solid-state reactions at 150 °C between Zn-doped Sn–20In solders and Ag and Ni substrates are investigated. In Sn–20In–xZn/Ag couples, when the Zn-doping level is low (x ≤ 1.0), the reaction path is γ-InSn4/ζ-AgZn/ζ-(Ag,In)/ζ-AgZn/Ag, that the ζ-AgZn layer near the solder has non-uniform composition, the ζ-(Ag,In) layer has a porous microstructure, and the ζ-AgZn phase near the substrate is composed of small grains. When the Zn doping level is high (x ≥ 2.0), the reaction path becomes γ-InSn4/ε-AgZn3/γ-Ag5Zn8/ζ-AgZn/Ag, that all intermetallic compounds (IMCs) are planar and neither Sn nor In participate in the reactions. Although the reactions are very sensitive to Zn contents, the overall thicknesses of IMCs do not vary much with different Zn-doping levels. In Sn–20In–xZn/Ni couples, the planar Ni5Zn21 phase is the only reaction product with a very slow growth rate. The interfacial liquation in Sn–20In/Ni contacts can be fully mitigated with a minor Zn addition of 0.5 wt.%.

An RDL UBM Structural Design for Solving Ultralow-K Delamination Problem of Cu Pillar Bump Flip Chip BGA Packaging

Copper (Cu) pillar bumps tend to induce high thermal–mechanical stress during environmental tests and fabrication processes due to the high hardness of Cu, especially when applied with an ultralow-K (ULK) chip. A previous experiment showed that interfacial delamination was often observed in the ULK layers of conventional Cu pillar bump-type flip chip ball grid array (FCBGA) packages under thermal cycling, where under bump metallurgy (UBM) layers directly sit on the metal pads of silicon chips (herein termed ‘‘direct UBM structure’’). In this study, a UBM pad relocation scheme through redistribution layer (RDL) technology (herein termed ‘‘RDL UBM structure’’) is proposed to relieve the stress or ULK delamination issue. The proposed technique is tested on Cu pillar bump-type FCBGA packages subjected to thermal loading, the effectiveness of which is demonstrated through finite element stress simulation and experimental reliability tests. Simulation results reveal that the RDL UBM structure can greatly reduce the maximum stress in the ULK layers by as much as about 10% to 44%. Besides, it turns out that the Cu pillar bump-type FCBGA packages with the RDL UBM structure show good interconnect reliability performance in terms of thermal cycling, highly accelerated stress, and high-temperature storage.